公开(公告)号：US12125888B2

公开(公告)日：2024-10-22

申请号：US16642861

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/41725 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US12027613B2

公开(公告)日：2024-07-02

申请号：US16419179

申请日：2019-05-22

申请人： Intel Corporation

发明人： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC分类号： H01L29/778 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L29/20 ,  H01L29/51

CPC分类号： H01L29/7786 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0655 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/778 ,  H01L2224/0401 ,  H01L2924/13064

摘要： Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

申请人： Intel Corporation

发明人： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

摘要： Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

申请人： Intel Corporation

发明人： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC分类号： H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

摘要： Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC分类号： H01L29/78 ,  H01L29/51

CPC分类号： H01L29/78391 ,  H01L29/516

摘要： In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

公开(公告)号：US20230395717A1

公开(公告)日：2023-12-07

申请号：US17833045

申请日：2022-06-06

申请人： Intel Corporation

发明人： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092

CPC分类号： H01L29/7845 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/45 ,  H01L27/092

摘要： An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US11715790B2

公开(公告)日：2023-08-01

申请号：US16390819

申请日：2019-04-22

申请人： Intel Corporation

发明人： Nidhi Nidhi ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Yang Cao ,  Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Paul B. Fischer

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/49 ,  H01L29/45 ,  H01L21/02 ,  H01L29/808 ,  H01L29/10

CPC分类号： H01L29/7786 ,  H01L21/0254 ,  H01L21/02458 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/49 ,  H01L29/4925 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/808 ,  H01L29/1066

摘要： Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

公开(公告)号：US20230073078A1

公开(公告)日：2023-03-09

申请号：US17445856

申请日：2021-08-25

申请人： Intel Corporation

发明人： Willy Rachmady ,  Sudipto Naskar ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Marko Radosavljevic ,  Nicole K. Thomas ,  Patrick Morrow ,  Urusa Alaan

IPC分类号： H01L27/12

摘要： An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

公开(公告)号：US11575036B2

公开(公告)日：2023-02-07

申请号：US16651327

申请日：2017-09-28

申请人： Intel Corporation

发明人： Han Wui Then ,  Stephan Leuschner ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L21/285 ,  H01L21/765 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H03F3/21 ,  H03F3/45

摘要： Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

公开(公告)号：US11569233B2

公开(公告)日：2023-01-31

申请号：US17334425

申请日：2021-05-28

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Van H. Le ,  Jack T. Kavalieros

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L21/8238

摘要： Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.