公开(公告)号：US20230395717A1

公开(公告)日：2023-12-07

申请号：US17833045

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092

CPC classification number: H01L29/7845 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/45 ,  H01L27/092

Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US20230420562A1

公开(公告)日：2023-12-28

申请号：US17809329

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Munzarin F. Qayyum ,  Nicole K. Thomas ,  Rohit Galatage ,  Patrick Morrow ,  Jami A. Wiedemer ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66795

Abstract: Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.

公开(公告)号：US20230395718A1

公开(公告)日：2023-12-07

申请号：US17833050

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/7845 ,  H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/45

Abstract: An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US20240222376A1

公开(公告)日：2024-07-04

申请号：US18091714

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Jami A. Wiedemer ,  Munzarin F. Qayyum ,  Cheng-Ying Huang ,  Rohit V. Galatage ,  Evan A. Clinton

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Technologies for ribbon field-effect transistors with variable nanoribbon channel dimensions are disclosed. In an illustrative embodiment, a stack of semiconductor nanoribbons are formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively narrowed and/or thinned, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be narrowed and/or thinned. In other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be narrowed and/or thinned.

公开(公告)号：US20230420528A1

公开(公告)日：2023-12-28

申请号：US17851658

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Patrick Morrow ,  Marko Radosavljevic ,  Jami A. Wiedemer ,  Subrina Rafique ,  Mauro J. Kobrinsky

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/0847 ,  H01L29/401 ,  H01L27/088 ,  H01L29/0673

Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.

公开(公告)号：US20230395697A1

公开(公告)日：2023-12-07

申请号：US17831800

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Cheng-Ying Huang ,  Willy Rachmady ,  Rohit Galatage ,  Jami A. Wiedemer ,  David Bennett ,  Dincer Unluer ,  Venkata Aditya Addepalli

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0669 ,  H01L21/823807

Abstract: A semiconductor structure includes a second device stacked over a first device. In an example, the first device includes (i) a first source region, (ii) a first drain region, (iii) a body including a semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. The body can be, for instance, a nanoribbon, nanosheet, or nanowire. In an example, the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the second device lacks a continuous body extending laterally from the second source region to the second drain region.

公开(公告)号：US10304956B2

公开(公告)日：2019-05-28

申请号：US15038969

申请日：2013-12-27

Applicant: INTEL CORPORATION ,  Pratik A. Patel ,  Mark Y. Liu ,  Jami A. Wiedemer ,  Paul A. Packan

Inventor： Pratik A. Patel ,  Mark Y. Liu ,  Jami A. Wiedemer ,  Paul A. Packan

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/324 ,  H01L29/267

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

公开(公告)号：US20240222521A1

公开(公告)日：2024-07-04

申请号：US18091676

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Evan A. Clinton ,  Rohit V. Galatage ,  Cheng-Ying Huang ,  Jack T. Kavalieros ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jami A. Wiedemer

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Technologies for ribbon field-effect transistors with variable nanoribbon numbers are disclosed. In an illustrative embodiment, a stack of semiconductor nanoribbons is formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively removed, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be removed. In other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be removed.

公开(公告)号：US20230420460A1

公开(公告)日：2023-12-28

申请号：US17847628

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Patrick Morrow ,  Quan Shi ,  Rohit Galatage ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Jami A. Wiedemer ,  Gilbert Dewey ,  Mauro J. Kobrinsky ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L27/0924 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L23/481

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

公开(公告)号：US20230402513A1

公开(公告)日：2023-12-14

申请号：US17838646

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Rohit Galatage ,  Willy Rachmady ,  Subrina Rafique ,  Nitesh Kumar ,  Cheng-Ying Huang ,  Jami A. Wiedemer ,  Nicloe K. Thomas ,  Munzarin F. Qayyum ,  Patrick Morrow ,  Marko Radosavljevic ,  Mauro J. Kobrinsky

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

Abstract: An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region. In an example, the source region includes a first region, and a second region compositionally different from and above the first region. The source contact extends through the second region and extends within the first region. In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.