公开(公告)号：US20240363731A1

公开(公告)日：2024-10-31

申请号：US18768952

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20240363729A1

公开(公告)日：2024-10-31

申请号：US18764620

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Meng-Ku Chen ,  Ji-Yin Tsai ,  Jeng-Wei Yu ,  Yi-Fang Pai ,  Pei-Ren Jeng ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L29/0642 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785 ,  H01L27/0886 ,  H01L29/0847

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

公开(公告)号：US20240363717A1

公开(公告)日：2024-10-31

申请号：US18771674

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Chandrashekhar Prakash Savant

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/4916 ,  H01L29/1033 ,  H01L29/66545

Abstract: In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

公开(公告)号：US20240363715A1

公开(公告)日：2024-10-31

申请号：US18770177

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Yeh Chen ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/78696

Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.

公开(公告)号：US20240363443A1

公开(公告)日：2024-10-31

申请号：US18768122

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Hsueh-Chang Sung ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

公开(公告)号：US20240363431A1

公开(公告)日：2024-10-31

申请号：US18766881

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7834 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

公开(公告)号：US20240363424A1

公开(公告)日：2024-10-31

申请号：US18769858

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsin-Han Tsai ,  Wei-Chin Lee ,  Chia-Ching Lee ,  Hung-Chin Chung ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/42372

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US20240355906A1

公开(公告)日：2024-10-24

申请号：US18303989

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Hua Hsu ,  Chia-I Lin ,  Hsiu-Hao Tsao ,  Kai-Min Chien ,  Chen-Huang Huang ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66818

Abstract: Embodiments include a method and device resulting from the method, including using a radical oxidation process to oxidize a spacer layer which lines the opening after removing a dummy gate electrode. The oxidized layer is removed by an etching process. An STI region disposed below the dummy gate electrode may be partially etched.

公开(公告)号：US20240355904A1

公开(公告)日：2024-10-24

申请号：US18234502

申请日：2023-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chien CHENG ,  Guan-Lin CHEN ,  Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes depositing a spacer layer over an isolation region between adjacent fin structures, and the spacer layer is formed on sidewalls and tops of the fin structures. The method further includes forming a mask on the spacer layer between the fin structures, and the mask has a height substantially less than a height of the fin structures. The method further includes removing portions of the spacer layer and recessing the fin structures to form a spacer and to expose a portion of each fin structure, the spacer includes a first portion having a “U” shape disposed on the isolation region, and the portion of each fin structure has a top surface located at a level substantially below a top surface of the isolation region. The method further includes removing the mask.

公开(公告)号：US20240355898A1

公开(公告)日：2024-10-24

申请号：US18760032

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Lun Min ,  Chang-Miao Liu ,  Xu-Sheng Wu

IPC: H01L29/49 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76834 ,  H01L21/823468 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.