公开(公告)号：US20240363729A1

公开(公告)日：2024-10-31

申请号：US18764620

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Meng-Ku Chen ,  Ji-Yin Tsai ,  Jeng-Wei Yu ,  Yi-Fang Pai ,  Pei-Ren Jeng ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L29/0642 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785 ,  H01L27/0886 ,  H01L29/0847

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

公开(公告)号：US20240363443A1

公开(公告)日：2024-10-31

申请号：US18768122

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Hsueh-Chang Sung ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

公开(公告)号：US12131911B2

公开(公告)日：2024-10-29

申请号：US17844563

申请日：2022-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66636

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

公开(公告)号：US20240355906A1

公开(公告)日：2024-10-24

申请号：US18303989

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Hua Hsu ,  Chia-I Lin ,  Hsiu-Hao Tsao ,  Kai-Min Chien ,  Chen-Huang Huang ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66818

Abstract: Embodiments include a method and device resulting from the method, including using a radical oxidation process to oxidize a spacer layer which lines the opening after removing a dummy gate electrode. The oxidized layer is removed by an etching process. An STI region disposed below the dummy gate electrode may be partially etched.

公开(公告)号：US12125878B2

公开(公告)日：2024-10-22

申请号：US17350492

申请日：2021-06-17

Applicant: Kioxia Corporation

Inventor： Tomonari Shioda ,  Yasunori Oshima ,  Taichi Iwasaki ,  Shota Yamagiwa ,  Hiroto Saito

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/45

CPC classification number: H01L29/0847 ,  H01L27/1207 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/167 ,  H01L29/456

Abstract: A semiconductor device in an embodiment includes a substrate and a transistor. The transistor includes a source layer, a drain layer, a gate insulation film, a gate electrode, a contact plug and a first epitaxial layer. The source layer and the drain layer are provided in surface regions of the substrate, and contain an impurity. The gate insulation film is provided on the substrate between the source layer and the drain layer. The gate electrode is provided on the gate insulation film. The contact plug is provided so as to protrude to the source layer or the drain layer downward of a surface of the substrate. The first epitaxial layer is provided between the contact plug and the source layer or drain layer, and contains both the impurity and carbon.

公开(公告)号：US20240332399A1

公开(公告)日：2024-10-03

申请号：US18732393

申请日：2024-06-03

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20240332089A1

公开(公告)日：2024-10-03

申请号：US18741998

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US12107086B2

公开(公告)日：2024-10-01

申请号：US17705537

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Su-Hao Liu ,  Yan-Ming Tsai ,  Chung-Ting Wei ,  Ziwei Fang ,  Chih-Wei Chang ,  Chien-Hao Chen ,  Huicheng Chang

IPC: H01L27/092 ,  H01L21/265 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/165 ,  H01L29/66545

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.

公开(公告)号：US20240324228A1

公开(公告)日：2024-09-26

申请号：US18679408

申请日：2024-05-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chih-Chieh Yeh

IPC: H10B43/35 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H10B43/35 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/792

Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

公开(公告)号：US12087643B2

公开(公告)日：2024-09-10

申请号：US17813000

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko Jangjian ,  Tzu-Kai Lin ,  Chi-Cherng Jeng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.