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1.发明授权公开(公告)号：US11929115B2
公开(公告)日：2024-03-12
申请号：US17715959
申请日：2022-04-08
发明人： Jer-Fu Wang , Hung-Li Chiang , Yi-Tse Hung , Tzu-Chiang Chen , Meng-Fan Chang
IPC分类号： G11C8/00 , G11C11/412 , G11C11/419 , H10B10/00
CPC分类号： G11C11/412 , G11C11/419 , H10B10/12
摘要： A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.
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公开(公告)号：US11903334B2
公开(公告)日：2024-02-13
申请号：US17371123
申请日：2021-07-09
发明人： Hung-Li Chiang , Jer-Fu Wang , Chao-Ching Cheng , Tzu-Chiang Chen
CPC分类号： H10N70/8413 , H10B63/20 , H10N70/011 , H10N70/231 , H10N70/826
摘要： A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
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公开(公告)号：US11854594B2
公开(公告)日：2023-12-26
申请号：US17697951
申请日：2022-03-18
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
CPC分类号： G11C11/2273 , G06N3/063 , G11C11/2275 , G11C11/2277 , G11C11/54
摘要： A data processing method, a data processing circuit, and a computing apparatus are provided. In the method, data is obtained. A first value of a bit of the data is switched into a second value according to data distribution and an accessing property of memory. The second value of the bit is stored in the memory in response to switching the bit.
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公开(公告)号：US20240324228A1
公开(公告)日：2024-09-26
申请号：US18679408
申请日：2024-05-30
IPC分类号： H10B43/35 , H01L29/08 , H01L29/165 , H01L29/66 , H01L29/78 , H01L29/792
CPC分类号： H10B43/35 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/66833 , H01L29/7848 , H01L29/7851 , H01L29/792
摘要： A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
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公开(公告)号：US20240185913A1
公开(公告)日：2024-06-06
申请号：US18170462
申请日：2023-02-16
发明人： Hung-Li Chiang , Jer-Fu Wang , Iuliana Radu
IPC分类号： G11C11/412 , H01L23/48 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786 , H10B10/00
CPC分类号： G11C11/412 , H01L23/481 , H01L29/41733 , H01L29/42392 , H01L29/66545 , H01L29/78696 , H10B10/125
摘要： A memory device and a semiconductor die are provided. The memory device includes: a non-volatile storage device, with a first terminal coupled to a bit line; and an access transistor, configured to control electrical connection between a second terminal of the non-volatile storage device and a source line, and comprising an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) stacked on the NFET. A common source/drain terminal of the NFET and the PFET is coupled to the second terminal of the non-volatile storage device. Another common source/drain terminal of the NFET and the PFET is coupled to the source line. Further, gate terminals of the NFET and the PFET are coupled to different word lines.
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公开(公告)号：US20230309285A1
公开(公告)日：2023-09-28
申请号：US17703931
申请日：2022-03-24
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
IPC分类号： H01L27/11 , H01L29/78 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , H01L29/78391
摘要： A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.
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公开(公告)号：US20230240078A1
公开(公告)日：2023-07-27
申请号：US17827140
申请日：2022-05-27
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
IPC分类号： H01L27/1159 , H01L27/11587 , H01L29/51 , H01L29/66 , H01L29/78 , G11C5/06 , H01L21/28
CPC分类号： H01L27/1159 , H01L27/11587 , H01L29/516 , H01L29/66795 , H01L29/7851 , G11C5/063 , H01L29/78391 , H01L29/6684 , H01L29/40111 , H01L27/10844
摘要： A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
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公开(公告)号：US20230225218A1
公开(公告)日：2023-07-13
申请号：US17574549
申请日：2022-01-13
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
IPC分类号： H01L43/08 , H01L27/22 , H01L43/02 , H01L43/12 , H01L23/522
CPC分类号： H01L43/08 , H01L27/228 , H01L43/02 , H01L43/12 , H01L23/5226
摘要： A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.
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公开(公告)号：US20240365689A1
公开(公告)日：2024-10-31
申请号：US18764340
申请日：2024-07-04
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
CPC分类号： H10N70/231 , G11C13/0004 , H10N70/8828
摘要： The disclosure provides a memory device, a memory array, and an N-bit memory unit. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
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公开(公告)号：US20240315152A1
公开(公告)日：2024-09-19
申请号：US18669541
申请日：2024-05-21
发明人： Hung-Li Chiang , Jer-Fu Wang , Chao-Ching Cheng , Tzu-Chiang Chen
CPC分类号： H10N70/8413 , H10B63/20 , H10N70/011 , H10N70/231 , H10N70/826
摘要： A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
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