公开(公告)号：US20240292764A1

公开(公告)日：2024-08-29

申请号：US18653418

申请日：2024-05-02

Applicant: Toshiba Global Commerce Solutions, Inc.

Inventor： Timothy Crockett ,  Lester Bartus, JR.

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  G11C13/0004 ,  G11C13/0038 ,  H10B63/20 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8828 ,  G11C2013/009

Abstract: A non-volatile multi-bit storage device that includes a phase change material doped with n-type or p-type semiconductor impurities, a first set of electrodes ohmically coupled to the phase change material, a second set of electrodes configured to apply an electric field across the phase change material. To program the non-volatile multi-bit storage device, an electrical field is applied to the phase change material as crystal annealing cool down is performed. Application of the electric field during the crystal annealing cool down forms a rectified current path through the phase change material.

公开(公告)号：US12035543B2

公开(公告)日：2024-07-09

申请号：US17064099

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H10B63/00 ,  H10B53/20 ,  H10N70/20

CPC classification number: H10B63/845 ,  H10B53/20 ,  H10B63/20 ,  H10B63/22 ,  H10B63/24 ,  H10B63/80 ,  H10B63/84 ,  H10N70/235 ,  H10N70/245

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

公开(公告)号：US11980109B2

公开(公告)日：2024-05-07

申请号：US17051268

申请日：2019-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun Heub Song ,  Jae Kyeong Jeong

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/20 ,  H10B63/84 ,  H10N70/8413 ,  H10N70/8836

Abstract: Provided are a selection element which does not need an intermediate electrode and thus has improved integration, a phase-change memory device having the selection element, and a phase-change memory implemented so that the phase-change memory device has a highly integrated three-dimensional architecture.

公开(公告)号：US20240138155A1

公开(公告)日：2024-04-25

申请号：US18547502

申请日：2022-03-20

Applicant: Peiching LIN

Inventor： Peiching LING ,  Nanray WU

IPC: H10B61/00 ,  H01L23/528 ,  H10B63/00

CPC classification number: H10B61/10 ,  H01L23/528 ,  H10B63/20

Abstract: A non-volatile memory device includes: an insulation layer; a Schottky diode, which is formed on the insulation layer; a writing wire which is conductive and is electrically connected to a first end of the Schottky diode: a memory unit on the Schottky diode, the memory unit being electrically connected to a second end of the Schottky diode: and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the Schottky diode to write the data into the memory unit.

公开(公告)号：US11937437B2

公开(公告)日：2024-03-19

申请号：US17381911

申请日：2021-07-21

Applicant: Kioxia Corporation

Inventor： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US11903334B2

公开(公告)日：2024-02-13

申请号：US17371123

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8413 ,  H10B63/20 ,  H10N70/011 ,  H10N70/231 ,  H10N70/826

Abstract: A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.

公开(公告)号：US11830549B2

公开(公告)日：2023-11-28

申请号：US17855424

申请日：2022-06-30

Applicant: SK hynix Inc. ,  Industry-University Cooperation Foundation Hanyang University ERICA Campus

Inventor： Tae Jung Ha ,  Soo Gil Kim ,  Jeong Hwan Song ,  Tae Joo Park ,  Tae Jun Seok ,  Hye Rim Kim ,  Hyun Seung Choi

IPC: G11C13/00 ,  G11C11/16 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/0038 ,  G11C11/1697 ,  H10B63/20 ,  H10N70/841 ,  H10N70/8833

Abstract: Disclosed are a method of operating a selector device, a method of operating a nonvolatile memory apparatus to which the selector device is applied, an electronic circuit device including the selector device, and a nonvolatile memory apparatus. The method of operating the selector device controls access to a memory element, and includes providing the selector device including a switching layer and first and second electrodes disposed on both surfaces of the switching layer, which includes an insulator and a metal element, and applying a multi-step voltage pulse to the switching layer via the first and second electrodes to adjust a threshold voltage of the selector device, the multi-step voltage pulse including a threshold voltage control pulse and an operating voltage pulse. The operating voltage pulse has a magnitude for turning on the selector device, and the threshold voltage control pulse has a lower magnitude lower than the operating voltage pulse.

公开(公告)号：US20230326522A1

公开(公告)日：2023-10-12

申请号：US18332058

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Chih Huang ,  Jui-Yu Pan ,  Kuo-Chyuan Tzeng

IPC: G11C11/56 ,  H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: G11C13/0028 ,  G11C11/56 ,  G11C13/0026 ,  H10B63/20 ,  H10B63/80 ,  H10B63/84 ,  H10N70/063 ,  H10N70/8265

Abstract: Various embodiments of the present application are directed towards an integrated chip including a first conductive interconnect structure overlying a substrate. A first memory stack is disposed on the first conductive interconnect structure. A second conductive interconnect structure overlies the first memory stack. The second conductive interconnect structure is spaced laterally between opposing sidewalls of the first conductive interconnect structure. A third conductive interconnect structure is disposed on the first conductive interconnect structure. A top surface of the third conductive interconnect structure is vertically above the second conductive interconnect structure.

公开(公告)号：US11711082B2

公开(公告)日：2023-07-25

申请号：US17497968

申请日：2021-10-10

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H03K19/1776 ,  H01L27/22 ,  G11C11/16 ,  H03K19/0948 ,  H01L25/18 ,  G11C11/412 ,  H01L23/538 ,  H01L23/00 ,  G11C11/419 ,  H03K19/20 ,  H03K19/173 ,  G11C13/00 ,  G11C14/00 ,  H03K19/17728 ,  H01L23/498 ,  H10B10/00 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00 ,  H03K19/21

CPC classification number: H03K19/1776 ,  G11C11/1673 ,  G11C11/412 ,  G11C11/419 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C14/009 ,  G11C14/0081 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B10/15 ,  H10B61/00 ,  H10B61/10 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  G11C2213/15 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/83104 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H03K19/21 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014

Abstract: A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

公开(公告)号：US20240268126A1

公开(公告)日：2024-08-08

申请号：US18562739

申请日：2022-06-08

Applicant: NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： Yuanmin DU ,  Wen Siang LEW ,  Putu Andhita DANANJAYA ,  Siew Wei HOO ,  Weng Hong Hong LAI

IPC: H10B63/00 ,  H01L21/02

CPC classification number: H10B63/20 ,  H01L21/02565

Abstract: Provided is an electrically actuated resistive non-volatile memory. The resistive memory device comprises a first electrode, a second electrode, a buffer layer, and a primary memory layer. The primary memory layer comprises a first active layer, a second active layer, and a third active layer, wherein an oxygen gradient is configured across the primary memory layer. Methods of fabricating and operating such a memory device are also provided. The memory device advantageously provides for lower power consumption and more stable resistive switching.