公开(公告)号：US20240332306A1

公开(公告)日：2024-10-03

申请号：US18741863

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02658

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.

公开(公告)号：US12089412B2

公开(公告)日：2024-09-10

申请号：US16831623

申请日：2020-03-26

Applicant: INTEL NDTM US LLC

Inventor： Dong Ji ,  Guangyu Huang ,  Deepak Thimmegowda

IPC: H10B43/40 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/22 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02595 ,  H01L29/04 ,  H01L29/0634 ,  H01L29/16 ,  H01L29/22 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/7827 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A driver circuit for a three-dimensional (3D) memory device has a super junction structure as a field management structure. The super junction structure could be referred to as an extended junction structure, which distributes the electrical field of the junction between the vertical channel and the gate conductor for a string driver. The vertical channel includes a channel conductor to connect vertically between a source conductor and a drain conductor. The extended junction structure extends in parallel with the vertical channel conductor, extending vertically toward the drain conductor, having a height greater than a height of the gate conductor.

公开(公告)号：US12068227B2

公开(公告)日：2024-08-20

申请号：US18196988

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US12057312B2

公开(公告)日：2024-08-06

申请号：US17616170

申请日：2020-04-26

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai Cheng ,  Liyang Zhang

IPC: H01L21/02

CPC classification number: H01L21/0254 ,  H01L21/02428 ,  H01L21/02483 ,  H01L21/02513 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242

Abstract: The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

Applicant: Kioxia Corporation

Inventor： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US20240117487A1

公开(公告)日：2024-04-11

申请号：US18056800

申请日：2022-11-18

Applicant: National Applied Research Laboratories

Inventor： Shu-Ju Tsai ,  Yi-Cheng Lin

IPC: C23C16/26 ,  C23C16/48 ,  C23C16/513 ,  H01L21/02

CPC classification number: C23C16/26 ,  C23C16/48 ,  C23C16/513 ,  H01L21/02115 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/02595 ,  H01L21/02598

Abstract: A 2D layered thin film structure is disclosed. The 2D layered thin film structure can be applied to the growth of monocrystalline or polycrystalline group III nitrides and other 2D materials. The 2D layered thin film structure can be easily separated from the 2D layered thin film structure growth substrate, so that a single or composite nanopillar array structure formed by the monocrystalline or polycrystalline group III nitride or other 2D materials, or the 2D layered thin film structure can be transferred to any other substrate. In addition, the 2D layered thin film structure has excellent light transmittance, flexibility and component integration.

公开(公告)号：US11910602B2

公开(公告)日：2024-02-20

申请号：US17144562

申请日：2021-01-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun Liu ,  Zongliang Huo

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/311 ,  H01L29/10 ,  H10B43/35 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H10B43/27 ,  H01L21/02178 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/1037 ,  H10B43/35 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/40117

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

公开(公告)号：US11882703B2

公开(公告)日：2024-01-23

申请号：US17377117

申请日：2021-07-15

Applicant: SK hynix Inc.

Inventor： Sungmook Lim ,  Dae Hwan Yun ,  Gil Bok Choi ,  Jae Hyeon Shin ,  In Gon Yang ,  Hyung Jin Choi

IPC: H10B43/27 ,  H01L29/04 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H10B41/27 ,  H10B63/34

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

公开(公告)号：US20240021733A1

公开(公告)日：2024-01-18

申请号：US17813136

申请日：2022-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Julien Frougier ,  Ruilong Xie ,  Chanro Park

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L29/66803 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L21/02595

Abstract: A stacked semiconductor device includes stacked transistors. A lower transistor may be a p-type FinFET and an upper transistor vertically above the lower transistor may be a n-type nanostructure FET. The lower transistor may include a fin channel with a (110) orientated crystalline side surface. End surfaces of the fin channel contact a respective lower source/drain (S/D) region. The (110) orientated crystalline side surface may contact a lower gate structure. The upper transistor includes a diamond-shaped nano channel with a (111) orientated crystalline perimeter surface. End surfaces of the diamond-shaped nano channel may contact a respective upper S/D region. An upper gate structure may wrap around and contact the (111) orientated crystalline perimeter surface. An electrical isolation structure may separate the upper transistor from the lower transistor.

公开(公告)号：US20240021668A1

公开(公告)日：2024-01-18

申请号：US18335447

申请日：2023-06-15

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/04 ,  H01L21/02

CPC classification number: H01L29/04 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/02554 ,  H01L21/02129

Abstract: A semiconductor device includes an oxide semiconductor layer having a polycrystalline structure on an insulating surface, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first crystal structure overlapping the gate electrode and a second region having a second crystal structure not overlapping the gate electrode. An electrical conductivity of the second region is larger than an electrical conductivity of the first region. The second crystal structure is identical to the first crystal structure.