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公开(公告)号:US20240379865A1
公开(公告)日:2024-11-14
申请号:US18651909
申请日:2024-05-01
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU , Marina MOCHIZUKI , Ryo ONODERA , Masahiro WATABE
IPC: H01L29/786 , H01L29/417
Abstract: A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.
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公开(公告)号:US20240332427A1
公开(公告)日:2024-10-03
申请号:US18604840
申请日:2024-03-14
Applicant: Japan Display Inc.
Inventor: Marina MOCHIZUKI , Masahiro WATABE , Masashi TSUBUKU , Hajime WATAKABE , Toshinari SASAKI , Takaya TAMARU , Ryo ONODERA
IPC: H01L29/786 , H01L29/417 , H01L29/66
CPC classification number: H01L29/7869 , H01L29/41733 , H01L29/6675
Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.
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公开(公告)号:US20240312999A1
公开(公告)日:2024-09-19
申请号:US18588249
申请日:2024-02-27
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU , Marina MOCHIZUKI , Ryo ONODERA
IPC: H01L27/12
CPC classification number: H01L27/1225 , H01L27/1251
Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.
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公开(公告)号:US20240178325A1
公开(公告)日:2024-05-30
申请号:US18519392
申请日:2023-11-27
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU , Marina MOCHIZUKI , Ryo ONODERA
IPC: H01L29/786 , H01L29/06
CPC classification number: H01L29/7869 , H01L29/0603 , H01L29/78696
Abstract: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm−3.
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公开(公告)号:US20240105819A1
公开(公告)日:2024-03-28
申请号:US18474389
申请日:2023-09-26
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU
IPC: H01L29/66 , H01L21/02 , H01L29/786
CPC classification number: H01L29/66969 , H01L21/02667 , H01L29/7869
Abstract: A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.
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公开(公告)号:US20230387322A1
公开(公告)日:2023-11-30
申请号:US18449830
申请日:2023-08-15
Applicant: Japan Display Inc.
Inventor: Takaya TAMARU , Masashi TSUBUKU , Toshinari SASAKI , Hajime WATAKABE
IPC: H01L29/786 , H01L29/40 , H01L29/45
CPC classification number: H01L29/7869 , H10K59/1213 , H01L29/45 , H01L29/401
Abstract: A semiconductor device including: an oxide semiconductor layer including a first surface and a second surface opposite to the first surface; a gate electrode facing the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; and a pair of first electrode being in contact with the first surface of the oxide semiconductor layer, respectively, wherein the oxide semiconductor layer including a region in which composition ratio of nitrogen is 2 percent or more within a depth range of 2 nanometers from the first surface in a region vicinity of an edge of at least one of the first electrode of the pair of first electrode.
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公开(公告)号:US20230317833A1
公开(公告)日:2023-10-05
申请号:US18127661
申请日:2023-03-29
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU
IPC: H01L29/66 , H01L29/786 , H01L29/40 , H01L21/385
CPC classification number: H01L29/66969 , H01L29/7869 , H01L29/401 , H01L21/385 , H01L29/78696 , H01L29/42384
Abstract: A method for manufacturing semiconductor device according to an embodiment includes; forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.
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公开(公告)号:US20170269421A1
公开(公告)日:2017-09-21
申请号:US15448681
申请日:2017-03-03
Applicant: Japan Display Inc.
Inventor: Shinichiro OKA , Toshinari SASAKI
IPC: G02F1/1333 , G02F1/1362 , G02F1/1335 , G02F1/1368 , G02F1/1343 , G02F1/1339
CPC classification number: G02F1/133305 , G02F1/134363 , G02F1/13452 , G02F1/136209 , G02F1/1368 , G02F2001/13685
Abstract: An image display device includes a first substrate; a second substrate located to face the first substrate; an electro-optical layer between the first substrate and the second substrate; a plurality of pixel electrodes located between the electro-optical layer and the first substrate; a plurality of switching elements electrically connected with the plurality of pixel electrodes respectively; and a color filter included in a layer between the first substrate and the plurality of switching elements. A side of the first substrate opposite to a side thereof facing the electro-optical layer is an image display side.
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公开(公告)号:US20170005200A1
公开(公告)日:2017-01-05
申请号:US15186625
申请日:2016-06-20
Applicant: Japan Display Inc.
Inventor: Toshinari SASAKI
IPC: H01L29/786 , H01L27/12 , H01L29/423
CPC classification number: H01L27/1222 , H01L27/1225 , H01L27/1237 , H01L27/1251 , H01L29/41733 , H01L29/41741 , H01L29/42384 , H01L29/78642 , H01L29/78645 , H01L29/7869 , H01L29/78696
Abstract: A semiconductor device includes a first transistor including a first electrode, a first insulating layer above the first electrode, the first insulating layer having a first side wall, a first oxide semiconductor layer on the first side wall, the first oxide semiconductor layer being connected with the first electrode, a first gate electrode, a first gate insulating layer, and a second electrode above the first insulating layer, the second electrode being connected with the first oxide semiconductor layer; and a second transistor including a third electrode, a fourth electrode separated from the third electrode, a second oxide semiconductor layer between the third electrode and the fourth electrode, the second oxide semiconductor layer being connected with each of the third electrode and the fourth electrode, a second gate electrode, and a second gate insulating layer.
Abstract translation: 一种半导体器件,包括:第一晶体管,包括第一电极,第一电极上方的第一绝缘层,第一绝缘层,第一侧壁,第一侧壁上的第一氧化物半导体层,第一氧化物半导体层与 所述第一电极,第一栅电极,第一栅绝缘层和所述第一绝缘层上的第二电极,所述第二电极与所述第一氧化物半导体层连接; 以及第二晶体管,包括第三电极,与第三电极分离的第四电极,在第三电极和第四电极之间的第二氧化物半导体层,第二氧化物半导体层与第三电极和第四电极中的每一个连接, 第二栅极电极和第二栅极绝缘层。
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公开(公告)号:US20250015168A1
公开(公告)日:2025-01-09
申请号:US18894340
申请日:2024-09-24
Applicant: Japan Display Inc.
Inventor: Takaya TAMARU , Masashi TSUBUKU , Hajime WATAKABE , Toshinari SASAKI
IPC: H01L29/66 , G02F1/1368 , H01L21/02 , H01L29/786 , H10K59/121
Abstract: A method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component above an insulating surface; performing a planarization process on a surface of the first metal oxide layer; forming an oxide semiconductor layer on the insulating surface on which the planarization process is performed; forming a gate insulating layer above the oxide semiconductor layer; and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.
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