公开(公告)号：US20240339543A1

公开(公告)日：2024-10-10

申请号：US18743686

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Witold Kula ,  Gurtej S. Sandhu ,  John A. Smythe

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H10B99/00

CPC classification number: H01L29/78642 ,  H01L21/02178 ,  H01L21/02488 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78645 ,  H01L29/78696 ,  H10B99/00 ,  H01L21/0262

Abstract: An apparatus including an array of memory cells comprising transistors is disclosed. One or more of the transistors comprise a crystalline material extending substantially transverse to a base material. A gate dielectric material is adjacent to the crystalline material. A two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. The gate dielectric material overlies additional portions of the two-dimensional material of the channel region. One or more gates are adjacent to the gate dielectric material. An electronic device is also disclosed comprising one or more of the transistors. The one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. The channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.

公开(公告)号：US12108606B2

公开(公告)日：2024-10-01

申请号：US17892514

申请日：2022-08-22

Applicant: SK hynix Inc.

Inventor： Jae Hyun Han ,  Jae Gil Lee ,  Hyangkeun Yoo ,  Se Ho Lee

IPC: H10B51/20 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/7827 ,  H01L29/78391 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7889 ,  H10B51/10

Abstract: A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US12101946B2

公开(公告)日：2024-09-24

申请号：US18387921

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H10B99/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12075633B2

公开(公告)日：2024-08-27

申请号：US18317958

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yong-Jie Wu ,  Yen-Chung Ho ,  Mauricio Manfrini ,  Chung-Te Lin ,  Pin-Cheng Hsu

IPC: H10B63/00 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30 ,  H10B53/40 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/34 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869 ,  H10B53/30 ,  H10B53/40 ,  H10B63/80 ,  H10N70/011 ,  H10N70/231 ,  H10N70/24

Abstract: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.

公开(公告)号：US12057472B2

公开(公告)日：2024-08-06

申请号：US18050772

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L29/04 ,  H01L21/02 ,  H01L21/324 ,  H01L29/161 ,  H01L27/105 ,  H01L29/786

CPC classification number: H01L29/04 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/324 ,  H01L29/161 ,  H01L27/105 ,  H01L29/78642

Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US12040041B2

公开(公告)日：2024-07-16

申请号：US17448754

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: G11C5/02 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786 ,  H03K19/0948 ,  H10B63/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/44

CPC classification number: G11C5/025 ,  H01L21/308 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/66742 ,  H01L29/78642 ,  H03K19/0948 ,  H10B63/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/4401

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

公开(公告)号：US20240215217A1

公开(公告)日：2024-06-27

申请号：US18596501

申请日：2024-03-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Gerben DOORNBOS ,  Marcus Johannes Henricus VAN DAL

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/225 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B12/033 ,  H01L29/0673 ,  H01L29/225 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/315 ,  H10B12/395 ,  H10B12/482 ,  H01L2029/7858

Abstract: A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

公开(公告)号：US12021137B2

公开(公告)日：2024-06-25

申请号：US17578569

申请日：2022-01-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Oreste Madia

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02496 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/44 ,  H01L29/4908 ,  H01L29/78642 ,  H01L29/7869 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02488

Abstract: A method of forming a semiconductor device may include depositing a NiAl layer on a substrate, oxidizing the NiAl layer to form a bilayer including a NiO semiconducting material layer and an AlOx layer on the NiO semiconducting material layer, forming a semiconductor layer including the NiO semiconducting material layer, the semiconductor layer also including a channel region, and forming a gate dielectric on the channel region of the semiconductor layer.

公开(公告)号：US12002882B2

公开(公告)日：2024-06-04

申请号：US18157478

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7788 ,  H01L27/092 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/7831 ,  H01L29/78642

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

公开(公告)号：US20240153875A1

公开(公告)日：2024-05-09

申请号：US18054133

申请日：2022-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Koichi Motoyama ,  Chih-Chao Yang ,  Feng Liu

IPC: H01L23/528 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/28141 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0694 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78642

Abstract: A semiconductor device includes a first source/drain element on a first side of the semiconductor device, a second source/drain element on an opposing side of the semiconductor device, a backside contact including a first contact end on a first end of the first source/drain element and an opposing contact end in electrical communication with a backside power distribution network, a critical dimension of the first contact end is smaller than the critical dimension of the opposing contact end, and the backside contact is substantially aligned to the first source/drain element. The semiconductor device also includes and a source/drain placeholder material with a critical dimension of a middle portion of the source/drain placeholder material being larger than the critical dimension of both tend portions.