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1.发明授权公开(公告)号：US12119269B2
公开(公告)日：2024-10-15
申请号：US17824744
申请日：2022-05-25
IPC分类号： H01L21/8234 , H01L21/8238 , H01L23/528 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/786 , H01L29/792 , H10B12/00 , H10B51/30 , H10B53/30 , H10B63/00 , H10B99/00 , H01L21/311 , H01L21/768
CPC分类号： H01L21/823487 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823885 , H01L23/528 , H01L29/0847 , H01L29/1037 , H01L29/7827 , H01L29/785 , H01L29/78642 , H01L29/7926 , H10B12/395 , H10B51/30 , H10B53/30 , H10B63/34 , H10B99/00 , H01L21/31111 , H01L21/76802 , H01L21/76877
摘要： An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.
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2.发明公开公开(公告)号：US20240233797A1
公开(公告)日：2024-07-11
申请号：US18615490
申请日：2024-03-25
IPC分类号： G11C11/402 , G11C11/409 , H01L29/22 , H01L29/78 , H10B99/00
CPC分类号： G11C11/4023 , G11C11/409 , H01L29/22 , H01L29/7827 , H10B99/00
摘要： Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
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公开(公告)号：US12002889B2
公开(公告)日：2024-06-04
申请号：US18160208
申请日：2023-01-26
发明人： Kamal M. Karda , Haitao Liu
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/66666 , H01L29/6675 , H01L29/7869
摘要： A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.
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公开(公告)号：US11985806B2
公开(公告)日：2024-05-14
申请号：US16721380
申请日：2019-12-19
发明人： Kamal M. Karda , Srinivas Pulugurtha , Haitao Liu , Karthik Sarpatwari , Durai Vishak Nirmal Ramaswamy
IPC分类号： H01L27/108 , H10B12/00 , G11C11/402
CPC分类号： H10B12/01 , G11C11/4023
摘要： Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
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公开(公告)号：US20240074216A1
公开(公告)日：2024-02-29
申请号：US18387921
申请日：2023-11-08
发明人： Kamal M. Karda , Yi Fang Lee , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Ramanathan Gandhi , Karthik Sarpatwari , Scott E. Sills , Sameer Chhajed
IPC分类号： H10B99/00 , H01L27/092 , H01L27/12 , H01L29/24 , H01L29/267 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H10B99/00 , H01L27/092 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1259 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/66969 , H01L29/78642 , H01L29/7869
摘要： Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US11871589B2
公开(公告)日：2024-01-09
申请号：US17745298
申请日：2022-05-16
IPC分类号： H01L27/00 , H01L29/00 , H10B99/00 , H01L27/12 , H01L29/788 , H01L29/24 , H01L29/786
CPC分类号： H10B99/00 , H01L27/124 , H01L27/1225 , H01L27/1251 , H01L29/24 , H01L29/7869 , H01L29/7881 , H01L29/78672
摘要： Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.
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公开(公告)号：US20230361118A1
公开(公告)日：2023-11-09
申请号：US17661979
申请日：2022-05-04
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L27/092 , H01L29/7827
摘要： A microelectronic device comprises vertical inverter comprising a pillar structure vertically extending above a first conductive line. The pillar structure comprises a first vertical transistor vertically overlying and in electrical communication with the first conductive line, a second conductive line vertically overlying the first conductive line and electrically isolated from the first conductive line by a dielectric material, the second conductive line configured to be coupled to a ground structure, a second vertical transistor horizontally neighboring the first vertical transistor and in electrical communication with the second conductive line, the second vertical transistor horizontally spaced from the first vertical transistor by the dielectric material, and at least one electrode horizontally extending along a channel region of the first vertical transistor and an additional channel region of the second vertical transistor. Related microelectronic devices and electronic systems are also described.
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公开(公告)号：US20230299163A1
公开(公告)日：2023-09-21
申请号：US17655479
申请日：2022-03-18
发明人： Kamal M. Karda , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Karthik Sarpatwari , Richard E. Fackenthal
IPC分类号： H01L29/423 , H01L27/02 , H01L27/11 , G11C5/02 , H01L27/092
CPC分类号： H01L29/42372 , G11C5/025 , H01L27/0207 , H01L27/092 , H01L27/1104
摘要： An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.
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公开(公告)号：US20230262954A1
公开(公告)日：2023-08-17
申请号：US18137852
申请日：2023-04-21
摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.
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公开(公告)号：US20230178661A1
公开(公告)日：2023-06-08
申请号：US18160208
申请日：2023-01-26
发明人： Kamal M. Karda , Haitao Liu
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/6675 , H01L29/7869 , H01L29/66666
摘要： A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.
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