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    SEMICONDUCTOR STRUCTURE
    1.
    发明公开
    SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20240312791A1

    公开(公告)日：2024-09-19

    申请号：US18671641

    申请日：2024-05-22

    Applicant: Winbond Electronics Corp.

    Inventor： Kai JEN ,  Hsiang-Po LIU

    IPC: H01L21/311 ,  H10B12/00

    CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H10B12/01

    Abstract: A semiconductor structure includes a substrate, an insulating layer formed on the substrate, and a plurality of pairs of linear structures arranged in parallel and formed in the insulating layer, wherein each pair of linear structures has a first linear structure and a second linear structure. There is a first space S1 between an end portion of the first linear structure and an end portion of the second linear structure, there is a second space S2 between a center portion of the first linear structure and a center portion of the second linear structure, and the second space S2 is greater than the first space S1.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    2.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 审中-公开

    公开(公告)号：US20240251543A1

    公开(公告)日：2024-07-25

    申请号：US18623929

    申请日：2024-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

    IPC: H10B12/00 ,  G11C5/06 ,  H01L29/24

    CPC classification number: H10B12/20 ,  G11C5/063 ,  H01L29/24 ,  H10B12/01

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.

    Semiconductor structure with embedded capacitor
    5.
    发明授权
    Semiconductor structure with embedded capacitor 有权

    公开(公告)号：US11800698B2

    公开(公告)日：2023-10-24

    申请号：US17403992

    申请日：2021-08-17

    Applicant: International Business Machines Corporation

    Inventor： Ruilong Xie ,  Takashi Ando ,  Alexander Reznicek ,  Bahman Hekmatshoartabari

    IPC: H10B12/00 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H10B12/00 ,  H01L29/0665 ,  H01L29/42392 ,  H10B12/01

    Abstract: Techniques for fabricating semiconductor structures and devices with stacked structures having embedded capacitors are disclosed. In one example, a semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure further includes a capacitor structure disposed in the second region of the substrate. The capacitor structure includes a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate. The semiconductor structure further includes a stacked device disposed on the first region of the substrate. The stacked device includes a first transistor and a second transistor. At least a portion of the second transistor is disposed under at least a portion of the first transistor. The first transistor and the second transistor are each coupled to the capacitor conductor.

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    7.
    发明公开
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230262952A1

    公开(公告)日：2023-08-17

    申请号：US18015118

    申请日：2021-08-05

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Motomu KURATA ,  Tsutomu MURAKAWA ,  Ryo ARASAWA ,  Kunihiro FUKUSHIMA ,  Yasumasa YAMANE ,  Shinya SASAGAWA

    IPC: H10B12/00

    CPC classification number: H10B12/01

    Abstract: A semiconductor device with a small variation in transistor characteristics can be provided. A step of forming an opening in a structure body including an oxide semiconductor device to reach the oxide semiconductor device, a step of embedding a first conductor in the opening, a step of forming a second conductor in contact with a top surface of the first conductor, a step of forming a first barrier insulating film by a sputtering method to cover the structure body, the first conductor, and the second conductor, and a step of forming a second barrier insulating film over the first barrier insulating film by an ALD method are included. The first barrier insulating film and the second barrier insulating film each have a function of inhibiting hydrogen diffusion.

    Method of manufacturing dynamic random-access memory
    9.
    发明授权
    Method of manufacturing dynamic random-access memory 有权

    公开(公告)号：US11665879B2

    公开(公告)日：2023-05-30

    申请号：US17864411

    申请日：2022-07-14

    Applicant: Winbond Electronics Corp.

    Inventor： Kai Jen ,  Hao-Chuan Chang

    IPC: H01L21/74 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H10B12/02 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/01 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

    Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.

    Semiconductor structure with stacked capacitors
    10.
    发明授权
    Semiconductor structure with stacked capacitors 有权

    公开(公告)号：US12068361B2

    公开(公告)日：2024-08-20

    申请号：US17401523

    申请日：2021-08-13

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

    Inventor： BingYu Zhu ,  Hai-Han Hung ,  Yin-Kuei Yu

    IPC: H10B12/00 ,  H01L27/08 ,  H01L49/02

    CPC classification number: H01L28/82 ,  H01L27/0805 ,  H01L28/91 ,  H10B12/01 ,  H10B12/02 ,  H10B12/315

    Abstract: Provided are a semiconductor structure and a method for preparing the same. The method for preparing a semiconductor structure includes: a substrate is provided; a stacked structure is formed on the substrate; a first capacitor having a first bottom electrode, a first dielectric layer and a first top electrode is formed in the stacked structure, in which the first bottom electrode is of a columnar structure; and a second capacitor having a second bottom electrode, a second dielectric layer and a second top electrode is formed on the first capacitor, in which the second bottom electrode is of a concave structure. The second dielectric layer is formed between the second bottom electrode and the second top electrode, and the second dielectric layer is further formed between the second bottom electrodes of adjacent second capacitors.

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