公开(公告)号：US20250006433A1

公开(公告)日：2025-01-02

申请号：US18216479

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Elijah Karpov ,  Nazila Haratipour ,  Sou-Chi Chang ,  Tristan Tronic

IPC: H01G7/06 ,  H10B53/00

Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to ferroelectric capacitors having a hafnium-zirconium oxide film between the electrodes of the capacitor are discussed. The hafnium-zirconium oxide film is thin and has large crystallite grains. The thin large grain hafnium-zirconium oxide film having large grains is formed by depositing a thick hafnium-zirconium oxide film and annealing the thick hafnium-zirconium oxide film to establish the large grain size, and etching back the hafnium-zirconium oxide film to the desired thickness for deployment in the ferroelectric capacitor.

公开(公告)号：US12040378B2

公开(公告)日：2024-07-16

申请号：US17336149

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

CPC classification number: H01L29/516 ,  H01L29/151 ,  H01L29/221 ,  H01L29/945

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US11980037B2

公开(公告)日：2024-05-07

申请号：US16906217

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC: H10B53/30 ,  H01L21/768 ,  H01L23/522

CPC classification number: H10B53/30 ,  H01L21/7687 ,  H01L23/5226 ,  H01L21/76843

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

公开(公告)号：US20240112714A1

公开(公告)日：2024-04-04

申请号：US17957591

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Christopher Neumann ,  Brian Doyle ,  Sou-Chi Chang ,  Bernal Granados Alpizar ,  Sarah Atanasov ,  Matthew Metz ,  Uygar Avci ,  Jack Kavalieros ,  Shriram Shivaraman

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

CPC classification number: G11C11/221 ,  H01L27/11507 ,  H01L28/55

Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.

公开(公告)号：US11901400B2

公开(公告)日：2024-02-13

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC: H01L49/02 ,  H01G4/012 ,  H01G4/30 ,  H01L23/522 ,  H10B51/00

CPC classification number: H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US11742407B2

公开(公告)日：2023-08-29

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Sou-Chi Chang ,  Devin Merrill ,  I-Cheng Tung ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Ian A. Young ,  Matthew V. Metz ,  Uygar E. Avci ,  Chia-Ching Lin ,  Owen Loh ,  Shriram Shivaraman ,  Eric Charles Mattson

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/512 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20220416032A1

公开(公告)日：2022-12-29

申请号：US17358436

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena Nandi ,  Chi-Hing Choi ,  Gilbert Dewey ,  Harold Kennel ,  Omair Saadat ,  Jitendra Kumar Jha ,  Adedapo Oni ,  Nazila Haratipour ,  Anand Murthy ,  Tahir Ghani

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/768

Abstract: Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

公开(公告)号：US11063131B2

公开(公告)日：2021-07-13

申请号：US16440609

申请日：2019-06-13

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC: B81B3/00 ,  H01L21/00 ,  H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US20250006434A1

公开(公告)日：2025-01-02

申请号：US18883126

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H10B12/00

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.