公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

申请人： Intel Corporation

发明人： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

申请人： Intel Corporation

发明人： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

摘要： A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US11769789B2

公开(公告)日：2023-09-26

申请号：US16368450

申请日：2019-03-28

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC分类号： H01G4/30 ,  H10B51/00 ,  H01L23/522 ,  H01L49/02 ,  H01G4/012

CPC分类号： H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

摘要： A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

公开(公告)号：US20230193473A1

公开(公告)日：2023-06-22

申请号：US17559897

申请日：2021-12-22

申请人： Intel Corporation

发明人： Debaleena Nandi ,  Gilbert Dewey ,  Tahir Ghani ,  Nazila Haratipour ,  Mauro J. Kobrinsky ,  Anand Murthy

IPC分类号： C23C28/00 ,  H01L23/538

CPC分类号： C23C28/34 ,  C23C28/32 ,  C23C28/36 ,  H01L23/5383

摘要： The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.

公开(公告)号：US11626475B2

公开(公告)日：2023-04-11

申请号：US16441905

申请日：2019-06-14

申请人： INTEL CORPORATION

发明人： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ian A. Young ,  Uygar E. Avci ,  Jack T. Kavalieros

IPC分类号： H01L21/02 ,  H01L49/02 ,  H01G4/018 ,  H01L23/64

摘要： An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.

公开(公告)号：US11527656B2

公开(公告)日：2022-12-13

申请号：US16141408

申请日：2018-09-25

申请人： Intel Corporation

发明人： Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew Metz ,  Miriam Reshotko ,  Benjamin Chu-Kung ,  Shriram Shivaraman ,  Abhishek Sharma ,  Nazila Haratipour

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L27/24 ,  H01L29/66 ,  H01L27/108 ,  H01L29/45

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210408018A1

公开(公告)日：2021-12-30

申请号：US16914140

申请日：2020-06-26

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  I-Cheng Tung ,  Tobias Brown-Heft ,  Devin R. Merrill ,  Che-Yun Lin ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Matthew V. Metz

IPC分类号： H01L27/11502 ,  H01L49/02 ,  H01L27/08 ,  H01G4/008 ,  G11C11/22

摘要： An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

公开(公告)号：US20200286686A1

公开(公告)日：2020-09-10

申请号：US16296082

申请日：2019-03-07

申请人： Intel Corporation

发明人： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC分类号： H01G7/06 ,  H01L49/02 ,  H01L27/108

摘要： Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US12040378B2

公开(公告)日：2024-07-16

申请号：US17336149

申请日：2021-06-01

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC分类号： H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

CPC分类号： H01L29/516 ,  H01L29/151 ,  H01L29/221 ,  H01L29/945

摘要： Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US11980037B2

公开(公告)日：2024-05-07

申请号：US16906217

申请日：2020-06-19

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC分类号： H10B53/30 ,  H01L21/768 ,  H01L23/522

CPC分类号： H10B53/30 ,  H01L21/7687 ,  H01L23/5226 ,  H01L21/76843

摘要： Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.