公开(公告)号：US20240347619A1

公开(公告)日：2024-10-17

申请号：US18755327

申请日：2024-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Wen LIU ,  Chao-Hsiung WANG

IPC: H01L29/66 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L28/92 ,  H01L29/94 ,  H01L29/945

Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

公开(公告)号：US20240312874A1

公开(公告)日：2024-09-19

申请号：US18340873

申请日：2023-06-25

Applicant: SERIPHY TECHNOLOGY CORPORATION

Inventor： TZU-WEI CHIU ,  CHUN-WEI CHANG ,  WEI-CHIH CHEN ,  CHE-YEN HUANG

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L29/94

CPC classification number: H01L23/481 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L29/945 ,  H01L2224/0801 ,  H01L2224/08167 ,  H01L2224/32146 ,  H01L2225/06541 ,  H01L2924/1205 ,  H01L2924/1306 ,  H01L2924/1811

Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US12040379B2

公开(公告)日：2024-07-16

申请号：US18366596

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L29/66181 ,  H01L28/92 ,  H01L29/94 ,  H01L29/945

Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

公开(公告)号：US20240213377A1

公开(公告)日：2024-06-27

申请号：US18594215

申请日：2024-03-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Larry BUFFLE ,  Frédéric VOIRON ,  Sophie ARCHAMBAULT

IPC: H01L29/94

CPC classification number: H01L29/945 ,  H01L28/75 ,  H01L28/90 ,  H01L28/91

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

公开(公告)号：US20240186318A1

公开(公告)日：2024-06-06

申请号：US18526384

申请日：2023-12-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Joel METZ ,  Brice ARRAZAT

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0629 ,  H01L29/42336 ,  H01L29/66181 ,  H01L29/945

Abstract: An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.

公开(公告)号：US20240178055A1

公开(公告)日：2024-05-30

申请号：US18509190

申请日：2023-11-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Thierno Moussa BAH ,  Pascal GOURAUD ,  Patrick GROS D'AILLON ,  Emilie PREVOST

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768 ,  H01L29/94

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/30617 ,  H01L21/30625 ,  H01L21/76831 ,  H01L29/945

Abstract: The present description concerns a method of manufacturing an insulating trench in a substrate, for an electronic device, comprising the following successive steps: (a) filling a trench formed in the substrate with a first insulating material; (b) depositing a first etch stop layer on the first material; (c) depositing a second layer of a second insulating material on the first etch stop layer; (d) etching down to the etch stop layer; and (e) depositing a third layer made of a third tight material.

公开(公告)号：US11961921B2

公开(公告)日：2024-04-16

申请号：US17401484

申请日：2021-08-13

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Hiroshi Shibata

IPC: H01L29/92 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L29/945 ,  H01L29/66181

Abstract: A semiconductor device has a semiconductor substrate and a semiconductor film doped with impurities that is formed so as to cover an inner wall surface of a trench formed so as to extend from a first surface of the semiconductor substrate towards an interior thereof. The semiconductor film is formed so as to extend continuously from the inner wall surface to the first surface of the semiconductor substrate. The semiconductor device further has an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench. The semiconductor device further has an insulating film that insulates the semiconductor film from the opposite electrode.

公开(公告)号：US11948995B2

公开(公告)日：2024-04-02

申请号：US17911077

申请日：2021-01-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kazushi Yoshida ,  Yosuke Hagihara

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L29/0665 ,  H01L29/945

Abstract: A capacitor includes a silicon substrate, a conductor layer, and a dielectric layer. The silicon substrate has a principal surface including a capacitance generation region and a non-capacitance generation region. The silicon substrate includes a porous part provided in a thickness direction in the capacitance generation region. The conductor layer includes a surface layer part at least covering part of a surface of the capacitance generation region and a filling part filled in at least part of the porous part. The dielectric layer is provided between an inner surface of the porous part and the filling part. The porous part includes a macroporous part having macro pores and a nanoporous part formed in at least part of inner surfaces of the macro pores and having nano pores smaller than the macro pores.

公开(公告)号：US11888021B2

公开(公告)日：2024-01-30

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01L21/762 ,  H01L49/02 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/94 ,  H01L21/3215

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/324 ,  H01L21/32155 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US11854890B2

公开(公告)日：2023-12-26

申请号：US17188742

申请日：2021-03-01

Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  Friedrich-Alexander-Universitaet Erlangen-Nuernberg

Inventor： Florian Krach ,  Tobias Erlbacher

IPC: H01L29/92 ,  H01L21/78 ,  H01L29/66 ,  H01L29/94 ,  H01L27/06

CPC classification number: H01L21/78 ,  H01L29/66181 ,  H01L29/945 ,  H01L27/0694

Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.