公开(公告)号：US20240363587A1

公开(公告)日：2024-10-31

申请号：US18766684

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L21/563 ,  H01L21/6835 ,  H01L2221/68331 ,  H01L2221/68345

Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

公开(公告)号：US20240363549A1

公开(公告)日：2024-10-31

申请号：US18613040

申请日：2024-03-21

Applicant: Innolux Corporation

Inventor： Wei-Yuan Cheng ,  Ju-Li Wang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L23/367 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/33 ,  H01L25/16 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13105 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204

Abstract: An electronic device includes a substrate, a circuit layer, at least one electronic unit, a stress adjustment layer, and a buffer layer. The substrate has a first surface and a second surface opposite to each other and at least one side connected to the first surface and the second surface. The circuit layer is disposed on the first surface of the substrate. The at least one electronic unit is electronically connected to the circuit layer. The stress adjustment layer is disposed on the second surface of the substrate. The buffer layer surrounds the substrate, wherein the stress adjustment layer is located between the substrate and the buffer layer, and the buffer layer is in contact with the at least one side of the substrate.

公开(公告)号：US20240363543A1

公开(公告)日：2024-10-31

申请号：US18766974

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

公开(公告)号：US12132028B2

公开(公告)日：2024-10-29

申请号：US17698976

申请日：2022-03-18

Applicant: Amazon Technologies, Inc.

Inventor： Bassam Abdel-Dayem ,  Thomas A. Volpe

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/5386 ,  H01L23/642 ,  H01L25/50

Abstract: A semiconductor package can include a capacitance die. The package can have multiple dice (e.g., logic die, memory die) mounted on a substrate. Each die can include a power domain. The dice can be distributed on the substrate such that an extra space is present on the substrate between at least some of the dice. For example, an extra space may be present between two dice, at a corner of the substrate, or other locations. The extra space can disrupt a coplanarity of the semiconductor package. The capacitance die can be located in the extra space so as to establish the coplanarity with the other dice. The capacitance die can include a capacitor array electrically coupled to multiple power domains of the plurality of dice.

公开(公告)号：US12132004B2

公开(公告)日：2024-10-29

申请号：US17818797

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.

公开(公告)号：US20240355792A1

公开(公告)日：2024-10-24

申请号：US18137360

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Poh Boon KHOO ,  Jiun Hann SIR ,  Eng Huat GOH ,  Hooi San LAM ,  Hazwani JAFFAR

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments disclosed herein include electronic packages. In an example, an electronic package includes a package substrate. A die is coupled to the package substrate. The electronic package also includes a memory stack. The memory stack includes a die stack structure coupled to a substrate. The substrate is coupled to and is extending laterally beyond the package substrate. The die stack structure includes a stack of dies and through vias in a mold layer. The die stack structure is laterally spaced apart from the package substrate.

公开(公告)号：US20240355756A1

公开(公告)日：2024-10-24

申请号：US18762685

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/365

Abstract: Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.

公开(公告)号：US20240355754A1

公开(公告)日：2024-10-24

申请号：US18758423

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Kuo Lung Pan ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/023 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

公开(公告)号：US20240347515A1

公开(公告)日：2024-10-17

申请号：US18757531

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L23/291 ,  H01L24/97

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.

公开(公告)号：US20240347468A1

公开(公告)日：2024-10-17

申请号：US18754434

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.