公开(公告)号：US20240363587A1

公开(公告)日：2024-10-31

申请号：US18766684

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L21/563 ,  H01L21/6835 ,  H01L2221/68331 ,  H01L2221/68345

摘要： A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

公开(公告)号：US20220359458A1

公开(公告)日：2022-11-10

申请号：US17872023

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Chih-Wei Wu ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Cheng-Chieh Li

IPC分类号： H01L23/00

摘要： A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

公开(公告)号：US20220359357A1

公开(公告)日：2022-11-10

申请号：US17873168

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/053 ,  H01L23/00

摘要： A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.

公开(公告)号：US11476184B2

公开(公告)日：2022-10-18

申请号：US16723434

申请日：2019-12-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Pin-Tso Lin ,  Chia-Hsin Chen

IPC分类号： H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

摘要： A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

公开(公告)号：US20220293508A1

公开(公告)日：2022-09-15

申请号：US17827980

申请日：2022-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Ming Huang ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

公开(公告)号：US11437334B2

公开(公告)日：2022-09-06

申请号：US17097572

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC分类号： H01L23/00 ,  H01L23/498

摘要： A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.

公开(公告)号：US11081372B2

公开(公告)日：2021-08-03

申请号：US16712184

申请日：2019-12-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

摘要： A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP1. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP2, and LP2>LP1. The package system includes a first integrated circuit over the first interposer.

公开(公告)号：US10720401B2

公开(公告)日：2020-07-21

申请号：US16575573

申请日：2019-09-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20200003975A1

公开(公告)日：2020-01-02

申请号：US16451472

申请日：2019-06-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC分类号： G02B6/42 ,  H01L23/00

摘要： A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US10515829B2

公开(公告)日：2019-12-24

申请号：US15425282

申请日：2017-02-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

摘要： A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV) structures in and extending through the first substrate; a molding compound material surrounding the first substrate; at least one through via in the molding compound material with the through via being offset from the first substrate in a direction parallel to the first surface; a second interconnect structure over a second surface of the first substrate; and a first integrated circuit mounted over the first surface of the substrate, with the first integrated circuit being electrically coupled to at least one of the first TSV structures through the first interconnect structure and a connecting bump while the first interconnection structure is electrically coupled to the through via. The first interconnect structure may also be configured for mounting one or more integrated circuits and/or a second interposer on a surface opposite that of the first interposer.