公开(公告)号：US10720401B2

公开(公告)日：2020-07-21

申请号：US16575573

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20240021442A1

公开(公告)日：2024-01-18

申请号：US18362992

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Ting Chen ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih ,  Ting-Yu Yeh ,  Chen-Hsuan Tsai

IPC: H01L21/56 ,  H01L21/304 ,  H01L23/13 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L21/561 ,  H01L21/3043 ,  H01L23/13 ,  H01L23/3135 ,  H01L25/0655 ,  H01L25/18 ,  H01L21/563 ,  H01L23/147

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

公开(公告)号：US10304800B2

公开(公告)日：2019-05-28

申请号：US15800962

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Weiming Chris Chen ,  Ting-Yu Yeh ,  Chia-Hsin Chen ,  Tu-Hao Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498 ,  H01L25/16

Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.

公开(公告)号：US20190148329A1

公开(公告)日：2019-05-16

申请号：US15813538

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20240387197A1

公开(公告)日：2024-11-21

申请号：US18786580

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Ting Chen ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih ,  Ting-Yu Yeh ,  Chen-Hsuan Tsai

IPC: H01L21/56 ,  H01L21/304 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

公开(公告)号：US12062590B2

公开(公告)日：2024-08-13

申请号：US16725189

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ting-Yu Yeh ,  Chia-Hao Hsu ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Tu-Hao Yu ,  Shang-Yun Hou

IPC: H01L23/373 ,  H01L21/66 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/3735 ,  H01L22/32 ,  H01L23/562 ,  H01L24/17 ,  H01L27/0688 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

公开(公告)号：US20230386985A1

公开(公告)日：2023-11-30

申请号：US18359864

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Yu Yeh ,  Cing-He Chen ,  Kuo-Chiang Ting ,  Weiming Chris Chen ,  Chia-Hao Hsu ,  Kuan-Yu Huang ,  Shu-Chia Hsu

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0655

Abstract: A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.

公开(公告)号：US20220310411A1

公开(公告)日：2022-09-29

申请号：US17213241

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Ting Chen ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih ,  Ting-Yu Yeh ,  Chen-Hsuan Tsai

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L21/304

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

公开(公告)号：US09899305B1

公开(公告)日：2018-02-20

申请号：US15581667

申请日：2017-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ting-Yu Yeh ,  Wei-Ming Chen ,  Yi-Chiang Sun

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/34 ,  H01L23/367 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/17 ,  H01L2924/1816 ,  H01L2924/3511

Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.

公开(公告)号：US20230386969A1

公开(公告)日：2023-11-30

申请号：US17825336

申请日：2022-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Yu Yeh ,  Shu-Cheng Li ,  Chun-Hsien Wen ,  Chih-Wei Chang

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L23/5389 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/49816 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16225

Abstract: Connection structures and methods of manufacture in which a conductive structure is disposed between, and in electrical contact with, pluralities of via structures. Each via structure is laterally offset from adjacent via structures to avoid stacked vias, and each via is electrically connected to at least two additional vias on a level of a semiconductor device, through conductive traces and footprints of the connection structure.