公开(公告)号：US20220336364A1

公开(公告)日：2022-10-20

申请号：US17857066

申请日：2022-07-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ting Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Szu-Wei Lu

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

摘要： A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.

公开(公告)号：US11476184B2

公开(公告)日：2022-10-18

申请号：US16723434

申请日：2019-12-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Pin-Tso Lin ,  Chia-Hsin Chen

IPC分类号： H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

摘要： A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

公开(公告)号：US11373969B2

公开(公告)日：2022-06-28

申请号：US16989312

申请日：2020-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/532 ,  H01L29/06

摘要： An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

公开(公告)号：US11251071B2

公开(公告)日：2022-02-15

申请号：US16852987

申请日：2020-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  Jing-Cheng Lin ,  Hung-Jui Kuo

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L21/48

摘要： A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

公开(公告)号：US11018088B2

公开(公告)日：2021-05-25

申请号：US16436494

申请日：2019-06-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

摘要： An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.

公开(公告)号：US11004771B2

公开(公告)日：2021-05-11

申请号：US16390669

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Chieh Hsieh ,  Chi-Hsi Wu ,  Shin-Puu Jeng ,  Tsung-Yu Chen ,  Wensen Hung

IPC分类号： H01L23/427 ,  H01L23/367 ,  H01L23/373 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/34 ,  H01L23/31

摘要： Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.

公开(公告)号：US20210005556A1

公开(公告)日：2021-01-07

申请号：US17026597

申请日：2020-09-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  Wei-Cheng Wu

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/3105 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065

摘要： A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

公开(公告)号：US20200373266A1

公开(公告)日：2020-11-26

申请号：US16989312

申请日：2020-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

摘要： An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

公开(公告)号：US10720401B2

公开(公告)日：2020-07-21

申请号：US16575573

申请日：2019-09-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US10714426B2

公开(公告)日：2020-07-14

申请号：US16113665

申请日：2018-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Tsung-Shu Lin

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

摘要： An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.