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公开(公告)号:US20240363611A1
公开(公告)日:2024-10-31
申请号:US18766674
申请日:2024-07-09
发明人: Tsung-Shu Lin , Tsung-Yu Chen , Wensen Hung
CPC分类号: H01L25/18 , H01L23/3135 , H01L23/4006 , H01L23/46 , H01L23/49816 , H01L23/49833 , H01L24/16 , H01L2023/405 , H01L2023/4087 , H01L2224/16227
摘要: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
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公开(公告)号:US20230335449A1
公开(公告)日:2023-10-19
申请号:US18336960
申请日:2023-06-17
发明人: Wensen Hung , Yu-Ling Tsai , Chien-Chia Chiu , Tsung-Yu Chen
摘要: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.
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公开(公告)号:US20230071542A1
公开(公告)日:2023-03-09
申请号:US17700498
申请日:2022-03-22
发明人: Wensen Hung , Yih-Ting Shen , Jia-Syuan Li , Tsung-Yu Chen
IPC分类号: H01L23/367 , H01L25/065 , H01L23/498 , H01L23/00
摘要: A semiconductor device including a package, a lid and a thermal interface material is provided. The package includes a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies. The lid is disposed on the packaging substrate, the lid includes a cover portion and foot portion extending from the cover portion to the packaging substrate, wherein the cover portion covers the semiconductor dies and the insulating encapsulation, the foot portion includes foot segments laterally spaced apart from one another, and the foot segments are attached to the packaging substrate. The cover portion of the lid is attached to the package through the thermal interface material.
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公开(公告)号:US11587845B2
公开(公告)日:2023-02-21
申请号:US17396565
申请日:2021-08-06
发明人: Chi-Hsi Wu , Wensen Hung , Tsung-Shu Lin , Shih-Chang Ku , Tsung-Yu Chen , Hung-Chi Li
IPC分类号: H01L21/00 , H01L23/367 , H01L21/48 , H01L25/065 , H01L25/00 , H01L23/373
摘要: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.
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公开(公告)号:US20220149030A1
公开(公告)日:2022-05-12
申请号:US17584308
申请日:2022-01-25
发明人: Tsung-Shu Lin , Tsung-Yu Chen , Wensen Hung
摘要: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
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公开(公告)号:US11088048B2
公开(公告)日:2021-08-10
申请号:US16725255
申请日:2019-12-23
发明人: Chi-Hsi Wu , Wensen Hung , Tsung-Shu Lin , Shih-Chang Ku , Tsung-Yu Chen , Hung-Chi Li
IPC分类号: H01L21/00 , H01L23/367 , H01L21/48 , H01L25/065 , H01L25/00 , H01L23/373
摘要: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.
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公开(公告)号:US10978373B2
公开(公告)日:2021-04-13
申请号:US16290557
申请日:2019-03-01
发明人: Shih-Chang Ku , Hung-Chi Li , Tsung-Shu Lin , Tsung-Yu Chen , Wensen Hung
IPC分类号: H01L23/34 , H01L23/427 , H01L21/48 , H01L25/00 , H01L25/065
摘要: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
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公开(公告)号:US20200027809A1
公开(公告)日:2020-01-23
申请号:US16587463
申请日:2019-09-30
发明人: Wensen Hung , Szu-Po Huang , Hsiang-Fan Lee , Kim Hong Chen , Chi-Hsi Wu , Shin-Puu Jeng
IPC分类号: H01L23/36 , H01L23/04 , H01L23/10 , H01L25/065 , H01L23/367 , H01L23/42 , H01L23/498
摘要: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
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9.
公开(公告)号:US10269682B2
公开(公告)日:2019-04-23
申请号:US14880030
申请日:2015-10-09
发明人: Cheng-Chieh Hsieh , Chi-Hsi Wu , Shin-Puu Jeng , Tsung-Yu Chen , Wensen Hung
IPC分类号: H01L23/427 , H01L23/367 , H01L25/10 , H01L23/00 , H01L23/373 , H01L21/56 , H01L23/31
摘要: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.
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公开(公告)号:US20190096781A1
公开(公告)日:2019-03-28
申请号:US16206903
申请日:2018-11-30
发明人: Wensen Hung , Szu-Po Huang , Hsiang-Fan Lee , Kim Hong Chen , Chi-Hsi Wu , Shin-Puu Jeng
IPC分类号: H01L23/36 , H01L23/498 , H01L25/065 , H01L23/367 , H01L23/04 , H01L23/42 , H01L23/10 , H01L25/18 , H01L23/00
CPC分类号: H01L23/36 , H01L23/04 , H01L23/10 , H01L23/3675 , H01L23/3677 , H01L23/42 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/29011 , H01L2224/291 , H01L2224/2919 , H01L2224/29294 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/33519 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/83191 , H01L2224/92125 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/16153 , H01L2924/16251 , H01L2924/1679 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00 , H01L2924/014
摘要: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
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