公开(公告)号：US20240347508A1

公开(公告)日：2024-10-17

申请号：US18584007

申请日：2024-02-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jihyun Lim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L25/0655 ,  H01L23/041 ,  H01L23/3107 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06568

摘要： A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure; and an adhesive layer attaching the lower redistribution wiring layer and the encapsulation structure. The encapsulation structure includes a core substrate having a cavity formed therein, at least one semiconductor chip in the cavity such that a front surface on which chip pads are formed faces the lower redistribution wiring layer, and an upper redistribution wiring layer covering an upper surface of the core substrate and having upper redistribution wiring layers that are electrically connected to conductive structures of the core substrate.

公开(公告)号：US12119287B2

公开(公告)日：2024-10-15

申请号：US17288618

申请日：2019-09-20

申请人： Hitachi Astemo, Ltd.

发明人： Binti Haridan Fatin Farhanah ,  Takayuki Yogo ,  Hiroyuki Abe

IPC分类号： H01L23/49 ,  G01F5/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/495 ,  H01L29/84 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L23/495 ,  G01F5/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/49551 ,  H01L29/84 ,  H05K1/18 ,  H05K3/3421 ,  H05K3/3494 ,  H01L2224/83815 ,  H05K2203/043

摘要： To obtain a chip package positioning structure capable of adjusting a tilt and a position of a chip package with respect to the circuit board and reducing mounting variations. The chip package positioning and fixing structure that positions and fixes, to a circuit board 4, a chip package 5 in which a flow rate detection element 53 is sealed with a resin so that a detection portion is at least exposed, in which the chip package includes a solder fixation portion 52 that fixes the chip package to the circuit board by soldering, and a positioning portion 514 that performs positioning to the circuit board, and the positioning portion is provided closer to the flow rate detection element from the solder fixation portion.

公开(公告)号：US12100640B2

公开(公告)日：2024-09-24

申请号：US18328387

申请日：2023-06-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hao Chen ,  Hung-Yu Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/04 ,  H01L23/31 ,  H01L23/40

CPC分类号： H01L23/3737 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/4006 ,  H01L2023/4087

摘要： A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

公开(公告)号：US12087649B2

公开(公告)日：2024-09-10

申请号：US17794761

申请日：2021-01-06

申请人： KYOCERA Corporation

发明人： Shigenori Takaya

IPC分类号： H01L23/14 ,  H01L23/04

CPC分类号： H01L23/14 ,  H01L23/04

摘要： A wiring base includes an insulation base having a first surface, a first differential-wiring channel, and a second differential-wiring channel. The first and the second differential-wiring channels are on the first surface and arranged side by side in a first direction. The first differential-wiring channel includes a pair of first signal conductors extending in a second direction intersecting the first direction and a pair of first grounding conductors extending along the first signal conductors with the first signal conductors being interposed therebetween. The second differential-wiring channel includes a pair of second signal conductors extending in the second direction and a pair of second grounding conductors extending along the second signal conductors with the second signal conductors being interposed therebetween. The wiring base further includes a first film extending in the second direction and positioned between first and second grounding conductors adjacent to each other in plan of the first surface.

公开(公告)号：US12068259B2

公开(公告)日：2024-08-20

申请号：US18121568

申请日：2023-03-14

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Wei Da Lin ,  Meng-Jen Wang ,  Hung Chen Kuo ,  Wen Jin Huang

IPC分类号： H01L23/552 ,  H01L21/3213 ,  H01L21/56 ,  H01L23/04 ,  H01L23/31

CPC分类号： H01L23/552 ,  H01L21/32131 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3114

摘要： A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

公开(公告)号：US20240194544A1

公开(公告)日：2024-06-13

申请号：US18581213

申请日：2024-02-19

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Sang Jae Jang ,  Weilung Lu ,  Burt Barber ,  Adrian Arcedera ,  Shingo Nakamura

IPC分类号： H01L23/043 ,  H01L21/50 ,  H01L21/52 ,  H01L23/04 ,  H01L23/055 ,  H01L23/06 ,  H01L23/10 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/043 ,  H01L21/50 ,  H01L21/52 ,  H01L23/04 ,  H01L23/055 ,  H01L23/06 ,  H01L23/10 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49838

摘要： In one example, a semiconductor device comprises a substrate comprising a top side, a bottom side, and a conductive structure, a body over the top side of the substrate, an electronic component over the top side of the substrate and adjacent to the body, wherein the electronic component comprises an interface element on a top side of the electronic component, a lid over the interface element and a seal between the top side of the electronic component and the lid, and a buffer on the top side of the substrate between the electronic component and the body. Other examples and related methods are also disclosed herein.

公开(公告)号：US20240120294A1

公开(公告)日：2024-04-11

申请号：US18391891

申请日：2023-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Chin-Hua WANG ,  Kuang-Chun LEE ,  Po-Yao LIN ,  Shyue-Ter LEU ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367

CPC分类号： H01L23/562 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816

摘要： A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.

公开(公告)号：US11916001B2

公开(公告)日：2024-02-27

申请号：US16961774

申请日：2018-12-13

申请人： Mitsubishi Electric Corporation

发明人： Kozo Harada

IPC分类号： H01L23/498 ,  H01L23/04 ,  H01L23/14 ,  H01L23/31 ,  H02M7/5387 ,  H02P27/08

CPC分类号： H01L23/49811 ,  H01L23/041 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3135 ,  H02M7/53871 ,  H02P27/08

摘要： A semiconductor power module includes a base plate, an insulating substrate, a power semiconductor element, an external terminal, a main terminal, a connected body, a case, a highly-insulating voltage-resisting resin material, a sealing resin, and a cover. The main terminal is connected to the connected body. The connected body is directly joined to the metal plate. The connected body is provided with a receiving section in which the main terminal is received. The receiving section is provided with a slit portion. The slit portion extends from a lower end side of the receiving section toward an upper end side thereof. The lower end side is located on a side close to the insulating substrate. The upper end side is located opposite to the side close to the insulating substrate.

公开(公告)号：US20240063066A1

公开(公告)日：2024-02-22

申请号：US17891665

申请日：2022-08-19

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Tomita Yoshihiro ,  Adel A. Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi ,  Yi Shi ,  Batao Zhang ,  Wenhao Li ,  Feras Eid

IPC分类号： H01L23/04 ,  H01L25/065 ,  H01L23/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/46 ,  H01L23/367

CPC分类号： H01L23/041 ,  H01L25/0652 ,  H01L23/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/46 ,  H01L23/367 ,  H01L2224/08145 ,  H01L2224/05599 ,  H01L24/05 ,  H01L2224/80379 ,  H01L24/80 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/131 ,  H01L24/13 ,  H01L2224/29099 ,  H01L24/29

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

公开(公告)号：US20240047282A1

公开(公告)日：2024-02-08

申请号：US17817249

申请日：2022-08-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： JEN-YUAN CHANG

IPC分类号： H01L23/04 ,  H01L25/065 ,  H01L21/683 ,  H01L23/10 ,  H01L21/82

CPC分类号： H01L23/04 ,  H01L25/0652 ,  H01L21/6836 ,  H01L23/10 ,  H01L21/82 ,  H01L24/08

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a first chip and a second chip. The second chip is bonded over and electrically connected to the first chip. The second chip includes a seal ring disposed at a periphery of the second chip and within the second chip. From a top view, the second chip includes a first number of sides and the seal ring includes a second number of sides. The first number is greater than four, and the second number is equal to or greater than the first number.