公开(公告)号：US20240347508A1

公开(公告)日：2024-10-17

申请号：US18584007

申请日：2024-02-22

申请人： Samsung Electronics Co., Ltd.

发明人： Jihyun Lim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L25/0655 ,  H01L23/041 ,  H01L23/3107 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06568

摘要： A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure; and an adhesive layer attaching the lower redistribution wiring layer and the encapsulation structure. The encapsulation structure includes a core substrate having a cavity formed therein, at least one semiconductor chip in the cavity such that a front surface on which chip pads are formed faces the lower redistribution wiring layer, and an upper redistribution wiring layer covering an upper surface of the core substrate and having upper redistribution wiring layers that are electrically connected to conductive structures of the core substrate.

公开(公告)号：US12094728B2

公开(公告)日：2024-09-17

申请号：US18324686

申请日：2023-05-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zi-Jheng Liu ,  Yu-Hsiang Hu ,  Jo-Lin Lan ,  Sih-Hao Liao ,  Chen-Cheng Kuo ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Meng-Wei Chou

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

摘要： A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

公开(公告)号：US12087757B2

公开(公告)日：2024-09-10

申请号：US18344456

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC分类号： H01L25/04 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L22/14 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182 ,  H01L2924/35

摘要： In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

公开(公告)号：US20240282750A1

公开(公告)日：2024-08-22

申请号：US18413184

申请日：2024-01-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SEOKBEOM YONG ,  Kyungsuk Oh

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06568

摘要： A semiconductor package including a package substrate; an upper chip on the package substrate; a passive element chip between the upper chip and the package substrate; and a lower chip between the passive element chip and the package substrate, wherein the passive element chip includes a through electrode connected to the lower chip; and a plurality of passive elements on the through electrode, and the upper surface of the passive element chip is in contact with the lower surface of the upper chip.

公开(公告)号：US12046529B2

公开(公告)日：2024-07-23

申请号：US18388873

申请日：2023-11-13

申请人： AMERICAN AXLE & MANUFACTURING, INC.

发明人： Jeffrey J. Ronning

IPC分类号： H01L23/367 ,  H01L23/36 ,  H01L25/065

CPC分类号： H01L23/3672 ,  H01L23/36 ,  H01L25/0652 ,  H01L2225/06562 ,  H01L2225/06568

摘要： An array of heat-sinked power semiconductors that includes a power semiconductor and a heat sink. The power semiconductor has a power semiconductor die, a plurality of first terminals and a second terminal. The power semiconductor die has a plurality of semiconductor terminals. Each of the first terminals is electrically coupled to an associated one of the semiconductor terminals. The second terminal is a surface mount terminal and is electrically coupled to one of the first terminals. The heat sink has a heat sink body and a plurality of fins. The heat sink body has a base and an exterior surface. The base is fixedly coupled directly to the surface mount terminal. The exterior surface has a fin mount portion to which the fins extend. At least a portion of the fin-mount portion is oriented non-parallel to base.

公开(公告)号：US20240203947A1

公开(公告)日：2024-06-20

申请号：US18586549

申请日：2024-02-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/89 ,  H01L25/50 ,  H01L28/60 ,  H01L2224/0557 ,  H01L2224/08146 ,  H01L2224/24145 ,  H01L2224/80001 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/19041

摘要： A package includes a first die, a second die, and an encapsulant. The first die includes a first capacitor. The second die includes a second capacitor. The second die is stacked on the first die. The first capacitor is spatially separated from the second capacitor. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.

公开(公告)号：US20240201439A1

公开(公告)日：2024-06-20

申请号：US18166460

申请日：2023-02-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng-Wei KUO ,  Wen-Shiang Liao

IPC分类号： G02B6/124 ,  G02B6/136 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： G02B6/1245 ,  G02B6/136 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  G02B2006/12104 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06568

摘要： A semiconductor package and a manufacturing method thereof are provided. A die stack in the semiconductor package includes a photonic die and an electronic die stacked on the photonic die by a face-to-face manner. A convex lens is disposed at a back surface of the electronic die, and is formed in an oval shape, such that optical beams can be collimated to have circular beam shape, as passing through the convex lens. In some embodiments, the semiconductor package includes more of the die stacks, and includes an interposer lying below the die stacks. In these embodiments, tilted reflectors are formed in the photonic dies and the interposer, to set up vertical optical paths between the interposer and the photonic dies, and lateral optical paths in the interposer. In this way, optical communication between the photonic dies can be established.

公开(公告)号：US20240178133A1

公开(公告)日：2024-05-30

申请号：US18434757

申请日：2024-02-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  An-Jhih Su ,  Li-Hsien Huang

IPC分类号： H01L23/522 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/5226 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L21/311 ,  H01L21/568 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181

摘要： Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

公开(公告)号：US20240162183A1

公开(公告)日：2024-05-16

申请号：US18422220

申请日：2024-01-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Jhih Mao ,  Kuei-Sung Chang ,  Shang-Ying Tsai

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/10 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/32 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/10 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/05 ,  H01L2224/05554 ,  H01L2224/1403 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17106 ,  H01L2224/17107 ,  H01L2224/26155 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/819 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06582

摘要： In some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. A first plurality of die stopper bumps are disposed along a backside of the first die. The first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. A plurality of adhesive structures are also present. Each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.

公开(公告)号：US11984342B2

公开(公告)日：2024-05-14

申请号：US17201284

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Kuei Cheng ,  Ching Fu Chang ,  Chih-Kang Han ,  Hsin-Chieh Huang

IPC分类号： H01L21/683 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L21/6835 ,  H01L21/288 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/351 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/94 ,  H01L2224/214 ,  H01L2224/97 ,  H01L2224/83

摘要： A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.