公开(公告)号：US20240313153A1

公开(公告)日：2024-09-19

申请号：US18481568

申请日：2023-10-05

申请人： Samsung Display Co., LTD.

发明人： Futoshi YOSHIDA ,  Jong Hyup KIM ,  Jin Pyung LEE ,  Chung Sic CHOI

IPC分类号： H01L33/00 ,  G01L1/24 ,  G06T7/90 ,  H01L23/00 ,  H01L25/075 ,  H01L33/62

CPC分类号： H01L33/0095 ,  G01L1/24 ,  G06T7/90 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0753 ,  H01L33/62 ,  G06T2207/10024 ,  G06T2207/10056 ,  G06T2207/30148 ,  H01L2224/32227 ,  H01L2224/75283 ,  H01L2224/7592 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83908 ,  H01L2924/12041 ,  H01L2924/1426 ,  H01L2933/0066

摘要： The disclosure provides a pressure detection method of a bonding device and a bonding system. The pressure detection method of a bonding device includes forming a backplane substrate including a light emitting element, disposing a pressure detection sheet on the backplane substrate, transferring the backplane substrate and the pressure detection sheet into a chamber, bonding the light emitting element by pressurizing the pressure detection sheet, photographing the pressure detection sheet, and detecting a color developing area of the pressure detection sheet. In the pressure detection method of the bonding device and the bonding system, it can be inspected whether uniform pressure is applied to a pressure detection sheet.

公开(公告)号：US12096554B2

公开(公告)日：2024-09-17

申请号：US17900309

申请日：2022-08-31

申请人： XEROX CORPORATION

发明人： Naveen Chopra ,  Barkev Keoshkerian ,  Chad Steven Smithson ,  Kurt I. Halfyard ,  Michelle N. Chretien

IPC分类号： H05K1/05 ,  B60R1/06 ,  B60R1/25 ,  C09D11/02 ,  C09D11/03 ,  C09D11/037 ,  C09D11/30 ,  C09D11/322 ,  C09D11/38 ,  C09D11/52 ,  G02F1/153 ,  G02F1/155 ,  G02F1/157 ,  G02F1/161 ,  H01B1/02 ,  H01B1/16 ,  H01B1/22 ,  H01L23/00 ,  H01L23/498 ,  H05K1/09 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K1/097 ,  C09D11/03 ,  C09D11/037 ,  C09D11/30 ,  C09D11/52 ,  H01B1/02 ,  H01B1/16 ,  H01B1/22 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H05K3/3457 ,  H01L2224/29239 ,  H01L2224/32227 ,  H01L2224/75155 ,  H01L2224/8384 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/14 ,  H05K3/3431 ,  H05K3/3485 ,  H05K3/3494 ,  H05K2201/0257

摘要： The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.

公开(公告)号：US20240258261A1

公开(公告)日：2024-08-01

申请号：US18629641

申请日：2024-04-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US11978714B2

公开(公告)日：2024-05-07

申请号：US18068064

申请日：2022-12-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L24/24 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/32227 ,  H01L2224/73267 ,  H01L2224/83001

摘要： A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20240105390A1

公开(公告)日：2024-03-28

申请号：US17951523

申请日：2022-09-23

申请人： WOLFSPEED, INC.

发明人： Kok Meng KAM ,  Eng Wah WOO ,  Samantha CHEANG ,  Marvin MARBELL ,  Haedong JANG ,  Jeremy FISHER ,  Basim NOORI

IPC分类号： H01G4/228 ,  H01L23/00 ,  H01L23/48 ,  H01L25/04 ,  H01L49/02

CPC分类号： H01G4/228 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/04 ,  H01L28/60 ,  H01L2224/05541 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/32227 ,  H01L2224/83815 ,  H01L2924/10272 ,  H01L2924/1205

摘要： In some aspects, a device includes a substrate. A first metallization arranged on the substrate. A second metallization arranged on the substrate. A circuit arranged on the substrate and electrically connected to the first metallization and the second metallization. The first metallization and the second metallization being configured, structured, and arranged to make a solder connection to a device, where the substrate may include silicon carbide (SiC).

公开(公告)号：US20240071963A1

公开(公告)日：2024-02-29

申请号：US17893968

申请日：2022-08-23

申请人： Micron Technology, Inc.

发明人： Yun Ting Hsu ,  Chong Leong Gan ,  Min Hua Chung ,  Yung Sheng Zou

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/05 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/2732 ,  H01L2224/32014 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/3207 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/83815 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

摘要： A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.

公开(公告)号：US11916008B2

公开(公告)日：2024-02-27

申请号：US17261756

申请日：2020-09-03

申请人： WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.

发明人： Yicheng Chen ,  Hong Wen

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/00

CPC分类号： H01L23/4985 ,  H01L21/4853 ,  H01L23/13 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32227 ,  H01L2224/83851

摘要： The present invention provides a chip-on-film (COF) packaging structure and a COF packaging method. The COF packaging structure includes a flexible substrate and a chip. The flexible substrate includes a first groove provided on a first surface of the flexible substrate, a protrusion provided in the first groove, and a substrate bonding pad disposed in the first groove. The chip includes a second groove provided on a second surface of the chip, and a chip bonding pad disposed on the second surface and corresponding to the substrate bonding pad. The first groove of the flexible substrate is matched with a peripheral shape of the chip, and the second groove is matched with the protrusion of the first groove to embed the chip in the flexible substrate. The chip bonding pad is electrically connected to the substrate bonding pad.

公开(公告)号：US20240063105A1

公开(公告)日：2024-02-22

申请号：US18185160

申请日：2023-03-16

申请人： BRIDGE SEMICONDUCTOR CORP.

发明人： Charles W. C. LIN ,  Chia-Chung WANG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L25/16 ,  H01L24/32 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L23/367 ,  H01L2224/32227 ,  H01L2224/06181 ,  H01L2224/0603 ,  H01L2224/37012 ,  H01L2224/40137 ,  H01L2224/40227

摘要： A semiconductor assembly includes a top substrate and a base substrate attached to top and bottom electrode layers of a semiconductor device, respectively. The top substrate includes an electrode connection plate thermally conductible with and electrically connected to the top electrode layer of the semiconductor device and vertical posts protruding from the electrode connection plate and electrically connected to the base substrate. The base substrate includes an electrode connection slug embedded in a dielectric layer and thermally conductible with and electrically connected to the bottom electrode layer of the semiconductor device and first and second routing circuitries deposited on two opposite surfaces of the dielectric layer, respectively, and electrically connected to each other.

公开(公告)号：US20240038743A1

公开(公告)日：2024-02-01

申请号：US17875647

申请日：2022-07-28

申请人： Avago Technologies International Sales Pte. Limited

发明人： Dingyou Zhang ,  Li Sun

IPC分类号： H01L25/16 ,  H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/162 ,  H05K1/183 ,  H05K1/181 ,  H01L21/563 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L24/13 ,  H01L23/3135 ,  H05K2201/10015 ,  H05K2201/1003 ,  H01L2924/15321 ,  H01L2924/3025 ,  H01L2924/2027 ,  H01L2924/182 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/19042 ,  H01L2924/19041 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48229 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/16148 ,  H01L2224/13005 ,  H01L2224/73265 ,  H01L2224/73253 ,  H01L2224/73215

摘要： A module is described. The module includes two dies which are stacked over a top insulating layer of a PCB. When both dies are be connected to the PCB through a copper pillar, the top die has a taller interconnect and the bottom die has a shorter interconnect. To further reduce a height of the module, the bottom die and/or the top die may be placed into a cavity of the PCB and a bulk silicon layer of the top die may be grinded away.

公开(公告)号：US11877485B2

公开(公告)日：2024-01-16

申请号：US17315456

申请日：2021-05-10

申请人： Samsung Display Co., Ltd.

发明人： Chung-seok Lee ,  Joonsam Kim ,  Chulho Jung

IPC分类号： H01L27/12 ,  H01K1/14 ,  H01L23/34 ,  H10K59/131 ,  H05K1/14 ,  H05K1/11 ,  H01L23/544 ,  H05K1/02 ,  H10K59/123 ,  H10K59/124 ,  H10K59/121 ,  H01L23/00 ,  H10K102/00

CPC分类号： H10K59/131 ,  H01L23/544 ,  H01L27/1262 ,  H05K1/0271 ,  H05K1/118 ,  H05K1/147 ,  H10K59/123 ,  H10K59/124 ,  H10K59/1213 ,  H01L24/29 ,  H01L24/32 ,  H01L27/124 ,  H01L27/1248 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/2929 ,  H01L2224/32227 ,  H01L2924/1304 ,  H05K2201/041 ,  H05K2201/09136 ,  H05K2201/09781 ,  H05K2201/10128 ,  H05K2201/10977 ,  H05K2203/166 ,  H10K2102/351 ,  H01L2924/00012

摘要： Provided is an electronic device including a display panel including a base substrate, pixels, a first insulation layer, and panel pads spaced along a first direction from pixels and each arranged along a second direction crossing the first direction, a circuit board disposed on the display panel and connected to panel pads, and an adhesive interconnect layer disposed between the display panel and the circuit board and electrically connecting the display panel and the circuit board. The circuit board includes a flexible substrate including a top surface facing the base substrate, output pads disposed on the flexible substrate and connected to panel pads, each obliquely extending in the first and second directions and arranged along the second direction, an alignment pad spaced along the second direction from output pads, and a stress relaxation pad disposed between output pads and alignment pads and electrically insulated from panel pads.