公开(公告)号：US20240363535A1

公开(公告)日：2024-10-31

申请号：US18771066

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L21/76892 ,  H01L29/401 ,  H01L29/41775 ,  H01L21/76885

Abstract: The semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, and a second dielectric feature. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner.

公开(公告)号：US12094764B2

公开(公告)日：2024-09-17

申请号：US17460978

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Chin Lee ,  Hsiao-Kang Chang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Cherng-Shiaw Tsai ,  Shao-Kuan Lee ,  Kuang-Wei Yang ,  Hsin-Yen Huang ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/53295

Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.

公开(公告)号：US20240290656A1

公开(公告)日：2024-08-29

申请号：US18655989

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20240274607A1

公开(公告)日：2024-08-15

申请号：US18641719

申请日：2024-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei WU ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H01L27/118 ,  G06F30/31 ,  G06F30/392 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/02 ,  H03K17/687

CPC classification number: H01L27/11807 ,  G06F30/31 ,  G06F30/392 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/0207 ,  H01L2027/11812 ,  H01L2027/11848 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11879 ,  H01L2027/11881 ,  H01L2027/11885 ,  H01L2027/11887 ,  H03K17/6872 ,  H03K17/6874

Abstract: A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

公开(公告)号：US12062603B2

公开(公告)日：2024-08-13

申请号：US18079555

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo

IPC: H01L23/498 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482

CPC classification number: H01L23/49827 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L21/28568 ,  H01L23/49866 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/95001 ,  H01L2924/35121

Abstract: Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.

公开(公告)号：US20240234299A1

公开(公告)日：2024-07-11

申请号：US18614755

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76885 ,  H01L21/78 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/37001

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

公开(公告)号：US20240222470A1

公开(公告)日：2024-07-04

申请号：US18428198

申请日：2024-01-31

Applicant: Texas Instruments Incorporated

Inventor： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC: H01L29/66 ,  C01G55/00 ,  H01L21/02 ,  H01L21/263 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/665 ,  C01G55/00 ,  C01G55/004 ,  H01L21/02068 ,  H01L21/2633 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/31122 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/53242 ,  H01L24/00 ,  H01L28/24 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835

Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

公开(公告)号：US20240222194A1

公开(公告)日：2024-07-04

申请号：US18604691

申请日：2024-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US12027495B2

公开(公告)日：2024-07-02

申请号：US17316044

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kun Sil Lee ,  Dong Kwan Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L25/50 ,  H01L21/7685 ,  H01L23/315 ,  H01L24/81 ,  H01L2221/101 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2225/06548

Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.

公开(公告)号：US12027479B2

公开(公告)日：2024-07-02

申请号：US16678134

申请日：2019-11-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jung-Hsing Chien

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L24/05 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/13 ,  H01L29/41725 ,  H01L29/4236 ,  H01L2224/0217 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/03019 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05573 ,  H01L2224/10135

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.