公开(公告)号：US20250070045A1

公开(公告)日：2025-02-27

申请号：US18403298

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yan-Zuo Tsai ,  Yang-Chih Hsueh

IPC: H01L23/00 ,  H01L23/482 ,  H01L23/498 ,  H01L25/065

Abstract: In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.

公开(公告)号：US12230559B2

公开(公告)日：2025-02-18

申请号：US18329347

申请日：2023-06-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. Carney ,  Jefferson W. Hall ,  Michael J. Seddon

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L27/146 ,  H01L29/08 ,  H02M3/158 ,  H01L23/14 ,  H01L23/15 ,  H01L23/367

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

公开(公告)号：US12221569B2

公开(公告)日：2025-02-11

申请号：US17440049

申请日：2019-10-30

Applicant: MODU TECH CO., LTD.

Inventor： Byeong Yeon Choi ,  Seung Yol Lee ,  Suk Hee Kang ,  Gyung Ju Yoon

IPC: C09J7/29 ,  C09J7/30 ,  C09J7/40 ,  C09J7/50 ,  C09J183/06 ,  H01L23/482

Abstract: Provided is an adhesive tape for a semiconductor package manufacturing process. The adhesive type includes: a first adhesive layer formed on a first base film; a second base film formed on the first adhesive layer, in which the second base film changes its shape to conform to the topology of the semiconductor package bottom surface when the adhesive tape is attached to the semiconductor package bottom surface, and containing a metal element so as to independently maintain the changed shape during the process; and a second adhesive layer formed on the second base film, the second adhesive layer having a smaller thickness than the first adhesive layer and having a lower adhesive strength than the first adhesive layer, wherein each of the first adhesive layer and the second adhesive layer has a spiral network molecular structure and includes a first adhesive composition containing silicone.

公开(公告)号：US12211916B2

公开(公告)日：2025-01-28

申请号：US17755029

申请日：2020-10-30

Applicant: Ampleon Netherlands B.V.

Inventor： Patrick Valk

IPC: H01L29/423 ,  H01L23/482 ,  H01L29/08 ,  H01L29/417 ,  H01L29/778 ,  H01L29/78

Abstract: Example embodiments relate to a field-effect transistors having improved layouts. One example field-effect transistor includes a semiconductor substrate on which at least one transistor cell array is arranged. Each transistor cell includes a first transistor cell unit. Each first transistor cell unit includes a plurality of gate fingers, a main gate finger segment, a plurality of drain fingers, and a main drain finger segment. Each first transistor cell unit also includes a main gate finger base connected to the main gate finger segment of the first transistor cell unit and extending from that main gate finger segment towards the main drain finger segment of that first transistor cell unit. Further, each first transistor cell unit includes a main drain finger base connected to the main drain finger segment of that first transistor cell and extending from that main drain finger segment towards that main gate finger segment.

公开(公告)号：US12183774B2

公开(公告)日：2024-12-31

申请号：US17417769

申请日：2019-02-22

Applicant: Mitsubishi Electric Corporation

Inventor： Shiro Hino ,  Junichi Nakashima ,  Takaaki Tominaga

IPC: H01L29/49 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H02M7/00

Abstract: To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

公开(公告)号：US20240404921A1

公开(公告)日：2024-12-05

申请号：US18439461

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Chengtar Wu

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes: a redistribution layer structure; first semiconductor and second dies on the redistribution, the second semiconductor die positioned next to the first semiconductor die; core balls positioned on the redistribution structure and next to the first semiconductor chip die; a bridge die configured to electrically connect the first and second semiconductor dies to each other on the first and second semiconductor dies; a substrate including an upper plate portion and a sidewall portion, the upper plate portion and the sidewall portion defining a cavity, the upper plate portion positioned on the bridge die, the side wall portion positioned on the core balls, the bridge die positioned within the cavity; and a molding material configured to mold the first semiconductor die, the second semiconductor die, the core balls, and the bridge die between the redistribution layer structure and the substrate.

公开(公告)号：US20240379504A1

公开(公告)日：2024-11-14

申请号：US18655631

申请日：2024-05-06

Applicant: Zhuhai YUEXIN Semiconductor Limited Liability Company

Inventor： XIANMING CHEN ,  LEI FENG ,  LINA JIANG ,  JUN GAO ,  BENXIA HUANG ,  WENJIAN LIN

IPC: H01L23/482 ,  H01L21/48 ,  H01L23/00 ,  H01L23/485 ,  H01L23/498

Abstract: A side-exposed embedded trace substrate includes a dielectric layer, a first wiring layer and a first wiring layer embedded in the dielectric layer. An outer surface of the first wiring layer is not higher than a surface of the dielectric layer, and the first wiring layer includes a pad having a groove to increase a side-exposed area of the pad. The contact area between the substrate and the solder during package welding is increased so that the welding reliability is enhanced, the problem of poor welding or poor reliability caused by trace embedding may be avoided, and poor filling of the packaging material due to insufficient gap between the device and the pad during packaging may be prevented.

公开(公告)号：US12113057B2

公开(公告)日：2024-10-08

申请号：US17225625

申请日：2021-04-08

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/84 ,  H01L23/482 ,  H01L23/66 ,  H01L27/06 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L27/0207 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/4824 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/41758

Abstract: A physical layout of a symmetric FET is described which provides symmetry in voltages coupled to structures of the FET so to reduce OFF state asymmetry in capacitances generated by the structures when the FET is used as a switch. According to one aspect, the symmetric FET is divided into two halves that are electrically coupled in parallel. Gate structures of the two half FETs are arranged in the middle region of the layout, each gate structure having gate fingers that project towards opposite directions. Interdigitated source and drain structures run along the gate fingers and include crossover structures that cross source and drain structures in the middle region of the layout. The gate structures share a body contact region that is arranged in the middle of the layout between the two gate structures.

公开(公告)号：US12087677B2

公开(公告)日：2024-09-10

申请号：US17248382

申请日：2021-01-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Clemens Ypil Quinones ,  Bigildis Dosdos ,  Jerome Teysseyre ,  Erwin Ian Vamenta Almagro ,  Romel N Manatad

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/482 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3142 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49568 ,  H01L23/544 ,  H01L23/562 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32258

Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.

公开(公告)号：US12062603B2

公开(公告)日：2024-08-13

申请号：US18079555

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo

IPC: H01L23/498 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482

CPC classification number: H01L23/49827 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L21/28568 ,  H01L23/49866 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/95001 ,  H01L2924/35121

Abstract: Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.