公开(公告)号：US20240363429A1

公开(公告)日：2024-10-31

申请号：US18771662

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC分类号： H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

摘要： A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

公开(公告)号：US20240363409A1

公开(公告)日：2024-10-31

申请号：US18771313

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

摘要： A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US12114492B2

公开(公告)日：2024-10-08

申请号：US17071980

申请日：2020-10-15

申请人： Micron Technology, Inc.

发明人： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC分类号： H10B43/27 ,  H01L21/285 ,  H10B41/27 ,  H10B43/10 ,  H10B41/10

CPC分类号： H10B41/27 ,  H01L21/28562 ,  H10B43/10 ,  H10B43/27 ,  H01L21/28518 ,  H01L21/28568 ,  H10B41/10

摘要： Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240332392A1

公开(公告)日：2024-10-03

申请号：US18737616

申请日：2024-06-07

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20240332023A1

公开(公告)日：2024-10-03

申请号：US18621828

申请日：2024-03-29

申请人： Applied Materials, Inc.

发明人： Ying-Bing JIANG ,  In Seok HWANG ,  Zhijun CHEN ,  Avgerinos V. GELATOS ,  Joung Joo LEE ,  Xianmin TANG ,  Fredrick FISHBURN ,  Le ZHANG ,  Wangee KIM ,  Mahendra PAKALA

IPC分类号： H01L21/285 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455

CPC分类号： H01L21/28518 ,  C23C16/24 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45557

摘要： The present disclosure relates to a method of selectively forming a silicide in high-aspect ratio structures by use of a multistep deposition process. A first precursor gas is delivered to a surface disposed within a processing region of a process chamber maintained at a first process pressure, where the substrate is maintained at a first temperature for a first period of time. A purge gas is delivered to for a second period of time after the first period of time has elapsed. A second precursor gas is delivered to the surface of the substrate. The second precursor being maintained at a second process pressure while the substrate is maintained at a second temperature for a third period of time. The purge gas is delivered to the processing region for a fourth period of time after the third period of time has elapsed.

公开(公告)号：US12087587B2

公开(公告)日：2024-09-10

申请号：US17325736

申请日：2021-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/28088 ,  H01L21/0259 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/0673

摘要： In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

公开(公告)号：US12063782B2

公开(公告)日：2024-08-13

申请号：US17941900

申请日：2022-09-09

申请人： Lodestar Licensing Group LLC

发明人： John D. Hopkins ,  Justin D. Shepherdson ,  Collin Howder ,  Jordan D. Greenlee

IPC分类号： H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L29/66 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC分类号： H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

摘要： Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US12062614B2

公开(公告)日：2024-08-13

申请号：US17374327

申请日：2021-07-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John Bruley ,  Jack O. Chu ,  Kam-Leung Lee ,  Ahmet S. Ozcan ,  Paul M. Solomon ,  Jeng-Bang Yau

IPC分类号： H01L23/535 ,  C22C30/00 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/78

CPC分类号： H01L23/535 ,  C22C30/00 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/7851 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

公开(公告)号：US12062579B2

公开(公告)日：2024-08-13

申请号：US17085850

申请日：2020-10-30

申请人： Applied Materials, Inc.

发明人： Xuebin Li

IPC分类号： H01L21/8238 ,  C23C16/42 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  H01L21/285

CPC分类号： H01L21/823814 ,  C23C16/42 ,  C23C16/50 ,  C23C16/52 ,  H01J37/3244 ,  H01J37/32715 ,  H01J37/32834 ,  H01J2237/3321 ,  H01L21/28518

摘要： A method and apparatus for the formation of a metal-oxide semiconductor FET (MOSFET) device is disclosed herein. The method of formation includes the utilization of a silicon-germanium seed layer deposited over an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductor (PMOS) device. The seed layer may be one seed layer deposited over both the NMOS source/drain regions and the PMOS source/drain regions or two doped seed layers wherein a first doped seed layer is deposited over the PMOS source/drain regions and a second doped seed layer is deposited over the NMOS source/drain regions. The seed layer enables simultaneous formation of a silicide over both the PMOS source/drain regions and the NMOS source/drain regions. The silicide formation consumes the seed layer and forms a silicide layer which varies in composition depending upon the composition of the absorbed seed layer.