公开(公告)号：US20240222276A1

公开(公告)日：2024-07-04

申请号：US18089877

申请日：2022-12-28

申请人： Intel Corporation

发明人： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC分类号： H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H05K1/18

CPC分类号： H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H05K1/181 ,  H05K2201/10159

摘要： Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

公开(公告)号：US20240221821A1

公开(公告)日：2024-07-04

申请号：US18089886

申请日：2022-12-28

申请人： Intel Corporation

发明人： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC分类号： G11C11/409 ,  H01L23/522 ,  H01L23/528

CPC分类号： G11C11/409 ,  H01L23/5226 ,  H01L23/5283

摘要： Structures having two-transistor gain cell are described. In an example, an integrated circuit structure includes a frontend device layer including a read transistor. A backend device layer is above the frontend device layer, the backend device layer including a write transistor. An intervening interconnect layer is between the backend device layer and the frontend device layer, the intervening interconnect layer coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.

公开(公告)号：US20240113116A1

公开(公告)日：2024-04-04

申请号：US17958293

申请日：2022-09-30

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  YenTing CHIU ,  Tahir GHANI ,  Leonard P. GULER ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Anand S. MURTHY ,  Wonil CHUNG ,  Allen B. GARDINER

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/092 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/775

摘要： Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

公开(公告)号：US20240014268A1

公开(公告)日：2024-01-11

申请号：US18370586

申请日：2023-09-20

申请人： Intel Corporation

发明人： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC分类号： H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66439

摘要： Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20230197722A1

公开(公告)日：2023-06-22

申请号：US17558026

申请日：2021-12-21

申请人： Intel Corporation

发明人： Mohammad HASAN ,  Mohit K. HARAN ,  Leonard P. GULER ,  Pratik PATEL ,  Tahir GHANI ,  Anand S. MURTHY ,  Makram ABD EL QADER

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

摘要： Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.

公开(公告)号：US20220131007A1

公开(公告)日：2022-04-28

申请号：US17569643

申请日：2022-01-06

申请人： Intel Corporation

发明人： Karthik JAMBUNATHAN ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Anand S. MURTHY ,  Tahir GHANI

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

摘要： Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

申请人： Intel Corporation

发明人： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

摘要： Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20220102522A1

公开(公告)日：2022-03-31

申请号：US17033499

申请日：2020-09-25

申请人： Intel Corporation

发明人： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Arnab SEN GUPTA ,  Christopher J. JEZEWSKI ,  I-Cheng TUNG ,  Matthew V. METZ ,  Anand S. MURTHY

IPC分类号： H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

摘要： Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

公开(公告)号：US20220102510A1

公开(公告)日：2022-03-31

申请号：US17033362

申请日：2020-09-25

申请人： Intel Corporation

发明人： Kevin COOK ,  Anand S. MURTHY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Ralph Thomas TROEGER ,  Christopher J. JEZEWSKI ,  I-Cheng TUNG

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238

摘要： Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.

公开(公告)号：US20210408285A1

公开(公告)日：2021-12-30

申请号：US16913294

申请日：2020-06-26

申请人： Intel Corporation

发明人： Ryan HICKEY ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Rushabh SHAH ,  Ju-Hyung NAM

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/786

摘要： Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.