公开(公告)号：US20220037530A1

公开(公告)日：2022-02-03

申请号：US17497864

申请日：2021-10-08

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Cory C. BOMBERGER ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088

摘要： Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US20190035897A1

公开(公告)日：2019-01-31

申请号：US16072313

申请日：2016-04-01

申请人： Intel Corporation

发明人： Chandra S. MOHAPATRA ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Will RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Matthew V. METZ ,  Sean T. MA

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/205 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

摘要： An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

公开(公告)号：US20180158737A1

公开(公告)日：2018-06-07

申请号：US15576248

申请日：2015-06-27

申请人： Intel Corporation

发明人： Seiyon KIM ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Karthik JAMBUNATHAN

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

摘要： A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.

公开(公告)号：US20220093797A1

公开(公告)日：2022-03-24

申请号：US17541199

申请日：2021-12-02

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Cory C. BOMBERGER ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

摘要： Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US20210408246A1

公开(公告)日：2021-12-30

申请号：US16911771

申请日：2020-06-25

申请人： Intel Corporation

发明人： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

摘要： Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US20210398979A1

公开(公告)日：2021-12-23

申请号：US17468522

申请日：2021-09-07

申请人： INTEL CORPORATION

发明人： Glenn A. GLASS ,  Anand S. MURTHY

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

摘要： Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

公开(公告)号：US20200303499A1

公开(公告)日：2020-09-24

申请号：US16085237

申请日：2016-03-30

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/66

摘要： Particular embodiments described herein provide for an electronic device that can include a nanowire channel. The nanowire channel can include nanowires and the nanowires can be about fifteen (15) or less angstroms apart. The nanowire channel can include more than ten (10) nanowires and can be created from a MXene material.

公开(公告)号：US20170222035A1

公开(公告)日：2017-08-03

申请号：US15487272

申请日：2017-04-13

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Anand S. MURTHY ,  Daniel B. AUBERTINE ,  Subhash M. JOSHI

IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

摘要： Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

申请人： Intel Corporation

发明人： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

摘要： Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20210408285A1

公开(公告)日：2021-12-30

申请号：US16913294

申请日：2020-06-26

申请人： Intel Corporation

发明人： Ryan HICKEY ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Rushabh SHAH ,  Ju-Hyung NAM

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/786

摘要： Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.