公开(公告)号：US20210091181A1

公开(公告)日：2021-03-25

申请号：US16580941

申请日：2019-09-24

申请人： Intel Corporation

发明人： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/78

摘要： Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20210408275A1

公开(公告)日：2021-12-30

申请号：US16913307

申请日：2020-06-26

申请人： Intel Corporation

发明人： Cory BOMBERGER ,  Suresh VISHWANATH ,  Pratik PATEL ,  Szuya S. LIAO ,  Anand S. MURTHY

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49

摘要： Integrated circuit structures having high surface germanium concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure has an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure has an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures.

公开(公告)号：US20210407851A1

公开(公告)日：2021-12-30

申请号：US16913320

申请日：2020-06-26

申请人： Intel Corporation

发明人： Cory BOMBERGER ,  Suresh VISHWANATH ,  Yulia TOLSTOVA ,  Pratik PATEL ,  Szuya S. LIAO ,  Anand S. MURTHY

IPC分类号： H01L21/768 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/08 ,  H01L29/66

摘要： Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.

公开(公告)号：US20240014268A1

公开(公告)日：2024-01-11

申请号：US18370586

申请日：2023-09-20

申请人： Intel Corporation

发明人： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC分类号： H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66439

摘要： Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20230197785A1

公开(公告)日：2023-06-22

申请号：US18110315

申请日：2023-02-15

申请人： Intel Corporation

发明人： Cory BOMBERGER ,  Anand MURTHY ,  Suresh VISHWANATH

IPC分类号： H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L23/00 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/0649 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2224/0401

摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US20200312958A1

公开(公告)日：2020-10-01

申请号：US16367134

申请日：2019-03-27

申请人： Intel Corporation

发明人： Anand MURTHY ,  Ryan KEECH ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00

摘要： Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20240332392A1

公开(公告)日：2024-10-03

申请号：US18737616

申请日：2024-06-07

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20210408258A1

公开(公告)日：2021-12-30

申请号：US16912118

申请日：2020-06-25

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20210399119A1

公开(公告)日：2021-12-23

申请号：US16910008

申请日：2020-06-23

申请人： Intel Corporation

发明人： Suresh VISHWANATH ,  Roza KOTLYAR ,  Han Wui THEN ,  Robert EHLERT ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Sandrine CHARUE-BAKKER

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66

摘要： Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.

公开(公告)号：US20200312959A1

公开(公告)日：2020-10-01

申请号：US16368097

申请日：2019-03-28

申请人： Intel Corporation

发明人： Cory BOMBERGER ,  Anand MURTHY ,  Suresh VISHWANATH

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L23/00

摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.