公开(公告)号：US20250072024A1

公开(公告)日：2025-02-27

申请号：US18237195

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alvin J. Joseph ,  Mark D. Levy ,  Rajendran Krishnasamy ,  Johnatan A. Kantarovsky ,  Ajay Raman ,  Ian A. McCallum-Cook

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/45 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.

公开(公告)号：US20250056837A1

公开(公告)日：2025-02-13

申请号：US18928429

申请日：2024-10-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Junichi KOEZUKA ,  Masami JINTYOU ,  Yukinori SHIMA ,  Takashi HAMOCHI ,  Yasutaka NAKAZAWA

IPC: H01L29/786 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1339 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/10 ,  H01L29/45 ,  H10K59/121

Abstract: A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.

公开(公告)号：US20250054766A1

公开(公告)日：2025-02-13

申请号：US18772359

申请日：2024-07-15

Applicant: Infineon Technologies Austria AG

Inventor： Clemens Ostermaier ,  Nicholas Dellas

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778

Abstract: A method includes: providing a Group III nitride-based substrate having a first major surface and a doped Group III nitride region; forming a first passivation layer configured as a hydrogen diffusion barrier on the first major surface; forming a first opening in the first passivation layer and exposing at least a portion of the doped Group III nitride region from the first passivation layer; activating a first doped Group III nitride region whilst the first passivation layer is located on the first major surface and the doped Group III nitride region is at least partly exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the doped Group III nitride region; forming a second opening in the first and second passivation layers and exposing a portion of the doped Group III nitride region; and forming a contact in the second opening.

公开(公告)号：US12218215B2

公开(公告)日：2025-02-04

申请号：US17681410

申请日：2022-02-25

Applicant: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION ,  KABUSHIKI KAISHA TOSHIBA

Inventor： Shunsuke Asaba ,  Yuji Kusumoto ,  Katsuhisa Tanaka ,  Yujiro Hara ,  Makoto Mizukami ,  Masaru Furukawa ,  Hiroshi Kono ,  Masanori Nagata

IPC: H01L29/45 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type on the first region, and a third silicon carbide region of a second conductivity type on the second region. Fourth and fifth silicon carbide region of the first conductivity type are on the third region. A first electrode has a first portion between the fourth region and fifth region in a first direction. A metal silicide layer is between the first portion and the third region, between the first portion and the fourth region in the first direction, and between the first portion and the fifth silicon carbide region in the first direction.

公开(公告)号：US12213323B2

公开(公告)日：2025-01-28

申请号：US18446557

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H10B61/00 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US12211920B2

公开(公告)日：2025-01-28

申请号：US17658771

申请日：2022-04-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Srinivasa Reddy Yeduru ,  Naveen Ganagona ,  George Chang ,  Byoungyong Park ,  Soonjae Lee

IPC: H01L29/45 ,  H01L21/265 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306

Abstract: In some aspects, the techniques described herein relate to a semiconductor device including: a substrate having a first side and a second side, the second side being opposite the first side; active circuitry disposed on the first side of the substrate; a metallic implant disposed in the substrate, the metallic implant being a blanket implant on the second side of the substrate; and a metallic layer disposed on the second side of the substrate, the metallic layer and the second side of the substrate including the metallic implant defining an ohmic contact.

公开(公告)号：US20250031429A1

公开(公告)日：2025-01-23

申请号：US18909063

申请日：2024-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jhih-Rong HUANG ,  Mrunal Abhijith KHADERBAD ,  Yi-Bo LIAO ,  Yen-Tien TUNG ,  Wei-Yen WOON

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45

Abstract: A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

公开(公告)号：US20250031425A1

公开(公告)日：2025-01-23

申请号：US18907260

申请日：2024-10-04

Applicant: Lawrence Livermore National Security, LLC

Inventor： Joel Basile Varley ,  Noah Patrick Allen ,  Clint Frye ,  Kyoung Eun Kweon ,  Vincenzo Lordi ,  Lars Voss

IPC: H01L29/20 ,  H01L21/225 ,  H01L29/45

Abstract: A method of electric field-enhanced impurity diffusion includes obtaining a heterostructure including a substrate of Group-III-nitride semiconductor material, a source layer including a dopant positioned directly on the substrate, and a conductive cap layer positioned above the source layer, and applying a thermal annealing treatment to the heterostructure. An electric field gradient is established within the source layer and the cap layer for causing diffusion of an element from the substrate to the cap layer, and for causing diffusion of the dopant from the source layer to a former location of the element in the substrate thereby changing a conductivity and/or magnetic characteristic of the substrate.

公开(公告)号：US12206019B2

公开(公告)日：2025-01-21

申请号：US17685257

申请日：2022-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Kanako Komatsu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L29/49 ,  H01L49/02

Abstract: According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.

公开(公告)号：US12205919B2

公开(公告)日：2025-01-21

申请号：US17555709

申请日：2021-12-20

Applicant: Infineon Technologies AG

Inventor： Chuan Cheah ,  Josef Hoeglauer ,  Tobias Polster

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00 ,  H01L25/07 ,  H01L29/40 ,  H01L29/45

Abstract: A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.