公开(公告)号：US20230139011A1

公开(公告)日：2023-05-04

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US20230207639A1

公开(公告)日：2023-06-29

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/401 ,  H01L29/7786 ,  H01L29/66462 ,  H01L29/41766 ,  H01L29/42316 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US20250072024A1

公开(公告)日：2025-02-27

申请号：US18237195

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alvin J. Joseph ,  Mark D. Levy ,  Rajendran Krishnasamy ,  Johnatan A. Kantarovsky ,  Ajay Raman ,  Ian A. McCallum-Cook

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/45 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.

公开(公告)号：US11121097B1

公开(公告)日：2021-09-14

申请号：US16881736

申请日：2020-05-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sebastian T. Ventrone ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Ajay Raman

IPC: H01L23/00 ,  H01L23/48

Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.

公开(公告)号：US11646351B2

公开(公告)日：2023-05-09

申请号：US17146513

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/49 ,  H01L29/47 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US20220223694A1

公开(公告)日：2022-07-14

申请号：US17146513

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11171095B1

公开(公告)日：2021-11-09

申请号：US16855185

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Ajay Raman ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Yves T. Ngu

IPC: H01L23/00

Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.

公开(公告)号：US12119383B2

公开(公告)日：2024-10-15

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/49 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11916119B2

公开(公告)日：2024-02-27

申请号：US17517738

申请日：2021-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhong-Xiang He ,  Jeonghyun Hwang ,  Ramsey M. Hazbun ,  Brett T. Cucci ,  Ajay Raman ,  Johnatan A. Kantarovsky

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/41783 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/7786

Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

公开(公告)号：US11437329B2

公开(公告)日：2022-09-06

申请号：US17070377

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.