公开(公告)号：US11901304B2

公开(公告)日：2024-02-13

申请号：US17323423

申请日：2021-05-18

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Sunil K. Singh ,  Vibhor Jain ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  Johnatan A. Kantarovsky ,  Yves T. Ngu

IPC分类号： H01L23/544 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/544 ,  H01L23/481 ,  H01L23/57 ,  H01L23/573 ,  H01L2223/5442 ,  H01L2223/54433

摘要： The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

公开(公告)号：US11749717B2

公开(公告)日：2023-09-05

申请号：US17738179

申请日：2022-05-06

申请人： GLOBALFOUNDRIES U.S. INC.

发明人： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

CPC分类号： H01L29/0653 ,  H01L21/763 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7841

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20230207639A1

公开(公告)日：2023-06-29

申请号：US18174052

申请日：2023-02-24

申请人： GlobalFoundries U.S. Inc.

发明人： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

CPC分类号： H01L29/401 ,  H01L29/7786 ,  H01L29/66462 ,  H01L29/41766 ,  H01L29/42316 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/4983

摘要： Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11380622B2

公开(公告)日：2022-07-05

申请号：US16953441

申请日：2020-11-20

申请人： GLOBALFOUNDRIES U.S. INC.

发明人： Vibhor Jain ,  Sunil K. Singh ,  Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Yves T. Ngu

IPC分类号： H01L23/544 ,  H01L23/00

摘要： The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

公开(公告)号：US12046633B2

公开(公告)日：2024-07-23

申请号：US17157269

申请日：2021-01-25

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Mark D. Levy ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Vibhor Jain

IPC分类号： H01L29/06 ,  H01L21/308 ,  H01L21/764 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08

CPC分类号： H01L29/0657 ,  H01L21/308 ,  H01L21/764 ,  H01L27/0635 ,  H01L27/0755 ,  H01L29/0653 ,  H01L29/0821

摘要： The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US20230037420A1

公开(公告)日：2023-02-09

申请号：US17386062

申请日：2021-07-27

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Brett T. Cucci ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778

摘要： The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.

公开(公告)号：US11574867B2

公开(公告)日：2023-02-07

申请号：US17104078

申请日：2020-11-25

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC分类号： H01L23/52 ,  H01L23/525 ,  H01L21/8249 ,  H01L21/02 ,  H01L27/07 ,  H01L23/62 ,  H01L27/115 ,  H01L27/112 ,  H01L27/02

摘要： An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20220165663A1

公开(公告)日：2022-05-26

申请号：US17104078

申请日：2020-11-25

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC分类号： H01L23/525 ,  H01L27/07 ,  H01L21/02 ,  H01L21/8249

摘要： An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US11646351B2

公开(公告)日：2023-05-09

申请号：US17146513

申请日：2021-01-12

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/49 ,  H01L29/47 ,  H01L29/45

CPC分类号： H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

摘要： Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US20220223694A1

公开(公告)日：2022-07-14

申请号：US17146513

申请日：2021-01-12

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

摘要： Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.