公开(公告)号：US20240363432A1

公开(公告)日：2024-10-31

申请号：US18767282

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76229 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US20240363417A1

公开(公告)日：2024-10-31

申请号：US18768844

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer DHANYAKUMAR ,  Huicheng CHANG ,  Keng-Chu LIN ,  Winnie Victoria Wei-Ning CHEN

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/092

Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

公开(公告)号：US12125911B2

公开(公告)日：2024-10-22

申请号：US17818595

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3065 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US12125876B2

公开(公告)日：2024-10-22

申请号：US15355783

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Cheng Wang ,  Han-Ti Hsiaw

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823878

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.

公开(公告)号：US20240347481A1

公开(公告)日：2024-10-17

申请号：US18753409

申请日：2024-06-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20240347389A1

公开(公告)日：2024-10-17

申请号：US18753024

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huan-Chieh SU ,  Li-Zhen YU ,  Chun-Yuan CHEN ,  Lo-Heng CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823437

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes first channel members over a first backside dielectric feature, second channel members over a second backside dielectric feature, a first epitaxial feature abutting the first channel members and over the first backside dielectric feature, a second epitaxial feature abutting the second channel members and over the second backside dielectric feature, a first gate structure wrapping around each of the first channel members, a second gate structure wrapping around each of the second channel members, and an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature. A bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.

公开(公告)号：US20240339406A1

公开(公告)日：2024-10-10

申请号：US18749812

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US12112987B2

公开(公告)日：2024-10-08

申请号：US18226185

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

公开(公告)号：US20240332022A1

公开(公告)日：2024-10-03

申请号：US18672104

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/31055 ,  H01L21/32136 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

公开(公告)号：US12107169B2

公开(公告)日：2024-10-01

申请号：US18349354

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.