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公开(公告)号：US20240332022A1
公开(公告)日：2024-10-03
申请号：US18672104
申请日：2024-05-23
发明人： Pei-Yu Wang , Zhi-Chang Lin , Ching-Wei Tsai , Kuan-Lun Cheng
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/3213 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66
CPC分类号： H01L21/28123 , H01L21/31055 , H01L21/32136 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/66545
摘要： A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.
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公开(公告)号：US11532626B2
公开(公告)日：2022-12-20
申请号：US16888537
申请日：2020-05-29
发明人： Jung-Hung Chang , Lo-Heng Chang , Zhi-Chang Lin , Shih-Cheng Chen , Kuo-Cheng Chiang , Chih-Hao Wang
IPC分类号： H01L29/78 , H01L27/092 , H01L21/02 , H01L21/8238 , H01L29/08 , H01L29/66 , H01L29/10
摘要： A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
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公开(公告)号：US11417777B2
公开(公告)日：2022-08-16
申请号：US16898717
申请日：2020-06-11
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L21/308 , H01L21/8234 , H01L29/786 , H01L29/66 , H01L21/3065 , H01L21/311 , H01L21/02
摘要： A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.
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公开(公告)号：US20220190137A1
公开(公告)日：2022-06-16
申请号：US17683251
申请日：2022-02-28
发明人： Chen-Han Wang , Ding-Kang Shih , Chun-Hsiung Lin , Teng-Chun Tsai , Zhi-Chang Lin , Akira Mineji , Yao-Sheng Huang
摘要： The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.
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公开(公告)号：US20220157994A1
公开(公告)日：2022-05-19
申请号：US17666240
申请日：2022-02-07
发明人： Shih-Cheng Chen , Kuo-Cheng Chiang , Zhi-Chang Lin
IPC分类号： H01L29/786 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66
摘要： A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.
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公开(公告)号：US20220130826A1
公开(公告)日：2022-04-28
申请号：US17568428
申请日：2022-01-04
发明人： Zhi-Chang Lin , Wei-Hao Wu , Jia-Ni Yu
IPC分类号： H01L27/092 , H01L27/02 , H01L27/11 , H01L29/08 , H01L21/8238 , H01L29/66 , H01L21/311
摘要： A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.
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公开(公告)号：US11315925B2
公开(公告)日：2022-04-26
申请号：US16932476
申请日：2020-07-17
发明人： Jui-Chien Huang , Shih-Cheng Chen , Chih-Hao Wang , Kuo-Cheng Chiang , Zhi-Chang Lin , Jung-Hung Chang , Lo-Heng Chang , Shi Ning Ju , Guan-Lin Chen
IPC分类号： H01L27/092 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/8234
摘要： According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
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公开(公告)号：US11309396B2
公开(公告)日：2022-04-19
申请号：US16683486
申请日：2019-11-14
发明人： Wei-Hao Wu , Zhi-Chang Lin , Ting-Hung Hsu , Kuan-Lun Cheng
IPC分类号： H01L29/423 , H01L29/66 , H01L29/786 , H01L27/092 , B82Y10/00 , H01L21/762 , H01L21/8238 , H01L21/8234 , H01L29/06 , H01L29/775 , H01L21/822 , H01L27/06 , H01L27/12 , H01L29/08 , H01L27/088
摘要： A semiconductor device includes a first device formed over a substrate. The first device includes a first gate stack encircling a first nanostructure, and the first device is a logic circuit device. The semiconductor device includes a second device formed over the first device. The second device includes a second gate stack encircling a second nanostructure, and the second device is a static random access memory (SRAM).
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公开(公告)号：US11264502B2
公开(公告)日：2022-03-01
申请号：US16803278
申请日：2020-02-27
发明人： Jung-Hung Chang , Lo-Heng Chang , Zhi-Chang Lin , Shih-Cheng Chen , Kuo-Cheng Chiang , Chih-Hao Wang
IPC分类号： H01L21/3065 , H01L27/092 , H01L29/66 , H01L21/28 , H01L21/8238 , H01L29/78 , H01L21/308 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/311
摘要： A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.
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10.发明授权公开(公告)号：US11217585B2
公开(公告)日：2022-01-04
申请号：US16279824
申请日：2019-02-19
发明人： Zhi-Chang Lin , Wei-Hao Wu , Jia-Ni Yu
IPC分类号： H01L27/092 , H01L27/02 , H01L27/11 , H01L29/08 , H01L21/8238 , H01L29/66 , H01L21/311
摘要： A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.
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