公开(公告)号：US20240347481A1

公开(公告)日：2024-10-17

申请号：US18753409

申请日：2024-06-25

申请人： STMicroelectronics (Rousset) SAS

发明人： Julien DELALLEAU ,  Christian RIVERO

IPC分类号： H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

摘要： An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20240347476A1

公开(公告)日：2024-10-17

申请号：US18632203

申请日：2024-04-10

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Howard E. CHEN ,  Robert Francis DARVEAUX

IPC分类号： H01L23/552 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

CPC分类号： H01L23/552 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/49 ,  H01L24/73 ,  H05K1/181 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2224/16141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K2201/10378 ,  H05K2201/10734

摘要： A method for implementing a packaged radio-frequency device is disclosed, including providing a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The method includes implementing a package on the first side of the packaging substrate, the package including a first overmold structure. The method further includes implementing a set of through-mold connections on the second side of the packaging substrate, the set of through-mold connections defining a mounting area on the second side of the packaging substrate. The method also includes mounting a component to the second side of the packaging substrate. The method additionally includes implementing a second overmold structure on the second side, the second overmold structure substantially encapsulating at least a portion of the component and including an underside surface.

公开(公告)号：US20240321774A1

公开(公告)日：2024-09-26

申请号：US18399519

申请日：2023-12-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kitae Park ,  Chiwan Song ,  Seonkyu Kim ,  Hyunna Bae ,  Seungmin Baek ,  Yongjae Song ,  Joonseok Oh ,  Jaewook Jung ,  Seokil Hong

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/31 ,  H01L23/492 ,  H01L25/065 ,  H10B80/00

CPC分类号： H01L23/562 ,  H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/32055 ,  H01L23/3135 ,  H01L23/4926 ,  H01L24/48 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/3511 ,  H01L2924/3512

摘要： The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.

公开(公告)号：US12057321B2

公开(公告)日：2024-08-06

申请号：US18446415

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien Wu

IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/04 ,  H01L29/786 ,  H01L21/324

CPC分类号： H01L21/32055 ,  H01L21/02595 ,  H01L21/0475 ,  H01L29/78672 ,  H01L21/02683 ,  H01L21/02686 ,  H01L21/324

摘要： A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.

公开(公告)号：US20240250126A1

公开(公告)日：2024-07-25

申请号：US18098999

申请日：2023-01-19

申请人： GlobalFoundries U.S. Inc.

发明人： Francois Hebert

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/02244 ,  H01L21/0332 ,  H01L21/32053 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827

摘要： Structures for a field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer. The gate conductor layer has a first portion disposed above the top surface of the semiconductor substrate and a second portion disposed inside the trench below the top surface of the semiconductor substrate.

公开(公告)号：US20240234370A1

公开(公告)日：2024-07-11

申请号：US18152130

申请日：2023-01-09

申请人： Wolfspeed, Inc.

发明人： Shadi Sabri

IPC分类号： H01L25/065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/77 ,  H01L23/14 ,  H01L23/16 ,  H01L23/31

CPC分类号： H01L25/0655 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0226 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32135 ,  H01L21/77 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3107

摘要： A semiconductor device and related fabrication method are disclosed. Specifically, a multi-layer structure in the semiconductor device is formed on a surface of a substrate and surrounded by a dicing street(s). The multi-layer structure can be formed to include an inter-layer dielectric (ILD) layer to act as an etch stop. A spacer dielectric layer is then deposited over the multi-layer structure and the surrounding dicing street(s). The spacer dielectric layer is then etched back to reveal the surrounding dicing street(s) while leaving in place a sidewall between multi-layer structure and the surrounding dicing street(s). By using the ILD layer to provide the etch stop, in conjunction with depositing the spacer dielectric layer before etching and leaving in place the sidewall after etching, it is possible to protect the multi-level structure for uncompromised integrity and performance.

公开(公告)号：US12009281B2

公开(公告)日：2024-06-11

申请号：US17586805

申请日：2022-01-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Chen ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Tin-Hao Kuo ,  Po-Yuan Teng ,  Chi-Hui Lai

IPC分类号： H01L23/367 ,  H01L21/3205 ,  H01L21/48 ,  H01L23/373 ,  H01L23/552 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

CPC分类号： H01L23/3677 ,  H01L21/32051 ,  H01L21/4882 ,  H01L23/3736 ,  H01L23/552 ,  H01L25/0655 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/18 ,  H01L2224/24137

摘要： A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

公开(公告)号：US20240179919A1

公开(公告)日：2024-05-30

申请号：US18436365

申请日：2024-02-08

申请人： SunRise Memory Corporation

发明人： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC分类号： H10B43/40 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B43/40 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2251 ,  H01L21/31111 ,  H01L21/32053 ,  H01L23/528 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78642 ,  H10B43/10 ,  H10B43/27

摘要： A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20240178003A1

公开(公告)日：2024-05-30

申请号：US18070030

申请日：2022-11-28

申请人： Tokyo Electron Limited

发明人： Hirokazu Aizawa ,  Kai-Hung Yu ,  Nicholas Joy ,  Yusuke Yoshida ,  Kandabara Tapily

IPC分类号： H01L21/3213 ,  G03F7/20 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3205

CPC分类号： H01L21/32133 ,  G03F7/70733 ,  H01L21/02164 ,  H01L21/02263 ,  H01L21/02318 ,  H01L21/0337 ,  H01L21/32051 ,  H01L21/32055

摘要： A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

公开(公告)号：US11991468B2

公开(公告)日：2024-05-21

申请号：US17861048

申请日：2022-07-08

申请人： Sony Group Corporation

发明人： Shinji Miyazawa

IPC分类号： H04N25/767 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L27/092 ,  H01L27/146 ,  H04N23/54 ,  H04N23/57 ,  H04N25/40 ,  H04N25/76

CPC分类号： H04N25/767 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0928 ,  H01L27/14621 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H04N23/54 ,  H04N23/57 ,  H04N25/40 ,  H04N25/76 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14645 ,  H01L2224/48463 ,  H01L2224/73257

摘要： The present disclosure relates to a solid-state imaging apparatus, a manufacturing method of the same and an electronic device which can make an apparatus size further smaller. A solid-state imaging apparatus includes: a laminate of a first structure in which a pixel array unit in which pixels that perform photoelectric conversion are two-dimensionally arranged is formed and a second structure in which an output circuit unit configured to output pixel signals output from the pixels to an outside of an apparatus is formed. The output circuit unit, a first through hole via which penetrates through a semiconductor substrate constituting part of the second structure, and an external terminal for signal output connected to the outside of the apparatus are disposed below the pixel array unit of the first structure. The present disclosure can be applied, for example, to a solid-state imaging apparatus or the like.