公开(公告)号：US20240355674A1

公开(公告)日：2024-10-24

申请号：US18763006

申请日：2024-07-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH ,  CHUN-CHI LAI

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/40 ,  H10B12/00

CPC classification number: H01L21/76843 ,  H01L21/28079 ,  H01L21/32135 ,  H01L29/401 ,  H10B12/482

Abstract: A method for fabricating a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, and forming a bit line structure over a S/D region of the semiconductor structure. The bit line structure includes a protection liner having a U-shaped profile and in direct contact with an upper portion of the gate dielectric layer. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

公开(公告)号：US12094877B2

公开(公告)日：2024-09-17

申请号：US18359492

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66492

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US20240290620A1

公开(公告)日：2024-08-29

申请号：US18638112

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Shu-Uei Jang ,  Ya-Yi Tsai ,  Ryan Chia-Jen Chen ,  An Chyi Wei ,  Shu-Yuan Ku

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/02164 ,  H01L21/32135 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

公开(公告)号：US12051621B2

公开(公告)日：2024-07-30

申请号：US17825405

申请日：2022-05-26

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L21/768 ,  B24B37/04 ,  B81B7/00 ,  B81C1/00 ,  C23F3/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/00 ,  C23F1/18 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L21/76868 ,  B24B37/042 ,  B81B7/0006 ,  B81C1/00095 ,  C23F3/00 ,  H01L21/30625 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76883 ,  H01L24/80 ,  H01L24/81 ,  C23F1/18 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/80031 ,  H01L2224/80895 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/1433 ,  H01L2924/00012 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

公开(公告)号：US12048162B2

公开(公告)日：2024-07-23

申请号：US18102917

申请日：2023-01-30

Applicant: LONGITUDE FLASH MEMORY SOLUTIONS LTD.

Inventor： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC: H10B43/30 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/792 ,  H10B43/27 ,  H10B43/40 ,  H10B99/00

CPC classification number: H10B43/30 ,  B82Y10/00 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/105 ,  H01L29/1033 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/4925 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B43/27 ,  H10B43/40 ,  H10B99/00

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

公开(公告)号：US20240213322A1

公开(公告)日：2024-06-27

申请号：US18599374

申请日：2024-03-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hongsheng YI ,  Hui SUN ,  Haolin HU ,  Biao GAO

IPC: H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/10 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/32135 ,  H01L21/32139 ,  H01L29/2003

Abstract: This application provides a field effect transistor, a preparation method, and an electronic circuit. During preparation, after a channel layer, a control gate layer, a metal gate layer, a hard mask layer, and a photoresist layer are sequentially formed on a substrate, a first photoresist mask pattern is formed. Dry etching is performed on the hard mask layer, to form a first hard mask pattern. Size shrinkage treatment is performed on the first photoresist mask pattern, to form a second photoresist mask pattern. A part, exposing the first hard mask pattern, of the second photoresist mask pattern forms a step surface. Dry etching is sequentially performed on the first hard mask pattern, the metal gate layer, and the control gate layer. During dry etching, the step surface extends downward and stops on a side wall of a control gate. The step surface may improve electrical leakage from the side wall.

公开(公告)号：US12014933B2

公开(公告)日：2024-06-18

申请号：US17562093

申请日：2021-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Yan-Hong Liu ,  Yeh-Chien Lin ,  Jin-Huai Chang

IPC: H01L21/3213 ,  H01L21/027 ,  H01L49/02

CPC classification number: H01L21/32135 ,  H01L21/0273 ,  H01L21/32139 ,  H01L28/20 ,  H01L28/60

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

公开(公告)号：US11967527B2

公开(公告)日：2024-04-23

申请号：US17843966

申请日：2022-06-18

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7685 ,  H01L21/76892 ,  H01L23/5226

Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

公开(公告)号：US20240096707A1

公开(公告)日：2024-03-21

申请号：US18521140

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Kuo-Bin Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L27/0924

Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

公开(公告)号：US20240021484A1

公开(公告)日：2024-01-18

申请号：US17947774

申请日：2022-09-19

Applicant: Changxin Memory Technologies, Inc.

Inventor： Mengmeng WANG ,  Yutong SHEN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215

CPC classification number: H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L21/28088 ,  H01L21/32135 ,  H01L21/3215

Abstract: A semiconductor structure and a preparation method therefor are provided. The semiconductor structure includes: a substrate, a gate dielectric layer, a first gate in a PMOS region, and a second gate in an NMOS region. The substrate includes a PMOS region and an NMOS region; the gate dielectric layer is located on the substrate of the PMOS region and of the NMOS region. The first gate includes a first work function layer and a first gate electrode layer that are stacked. The first work function layer is formed based on a first doping treatment of an initial work function layer. The second gate includes a second work function layer and a second gate electrode layer that are stacked. The semiconductor structure and the preparing method provided in the present disclosure can alleviate uneven etching of a PMOS transistor and an NMOS transistor and improve the yield and reliability of semiconductor devices.