公开(公告)号：US20190115461A1

公开(公告)日：2019-04-18

申请号：US16118603

申请日：2018-08-31

申请人： Kabushiki Kaisha Toshiba

发明人： Toshiya Yonehara ,  Tatsuo Shimizu ,  Hiroshi Ono ,  Daimotsu Kato

IPC分类号： H01L29/778 ,  H01L29/49 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L23/532 ,  H01L29/06

CPC分类号： H01L29/778 ,  H01L23/5329 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7786 ,  H01L29/78391

摘要： In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.

公开(公告)号：US20180026041A1

公开(公告)日：2018-01-25

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/792 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/1157 ,  H01L23/31 ,  H01L27/11582

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20170317097A1

公开(公告)日：2017-11-02

申请号：US15653661

申请日：2017-07-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Juergen Faul ,  Frank Jakubowski

IPC分类号： H01L27/11568 ,  H01L29/423 ,  H01L27/12 ,  H01L27/11521 ,  H01L21/762 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/265

CPC分类号： H01L27/11568 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/1207 ,  H01L28/00 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42336 ,  H01L29/42352

摘要： A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US09640626B2

公开(公告)日：2017-05-02

申请号：US15014586

申请日：2016-02-03

申请人： SK hynix Inc.

发明人： Jong-Han Shin

IPC分类号： H01L29/423 ,  H01L27/108 ,  H01L27/105

CPC分类号： H01L29/4236 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/42352 ,  H01L29/42356

摘要： A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.

公开(公告)号：US09589977B1

公开(公告)日：2017-03-07

申请号：US14963833

申请日：2015-12-09

申请人： United Microelectronics Corp.

发明人： Ko-Chi Chen ,  Shen-De Wang

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/28

CPC分类号： H01L27/1157 ,  H01L21/28088 ,  H01L21/28282 ,  H01L29/408 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

摘要： The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.

摘要翻译： 本发明提供了一种非易失性存储器及其制造方法。 非易失性存储器包括衬底，嵌入式电荷存储晶体管和选择晶体管。 基板有开口。 嵌入式电荷存储晶体管设置在基板中。 嵌入式电荷存储晶体管包括电荷存储结构和导电层。 电荷存储结构设置在开口中的基板上。 导电层设置在电荷存储结构上并填充开口。 选择晶体管设置在嵌入式电荷存储晶体管的一侧的衬底上，其中选择晶体管包括金属栅极结构。 非易失性存储器具有优异的电荷存储容量。

公开(公告)号：US09576974B2

公开(公告)日：2017-02-21

申请号：US14870164

申请日：2015-09-30

申请人： SK hynix Inc.

发明人： Sang Bum Lee

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/283

CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/31116 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66825 ,  H01L29/66833

摘要： A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately stacked, forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers are alternately stacked, forming preliminary holes penetrating the second stack structure, forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside the preliminary holes, and forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary holes to the first stack structure.

摘要翻译： 一种制造半导体器件的方法包括在下部结构上形成第一堆叠结构，其中第一材料层和第二材料层交替堆叠，在第一堆叠结构上形成第二堆叠结构，其中第三层和第四层 材料层交替堆叠，形成穿过第二堆叠结构的初步孔，形成覆盖第二堆叠结构上的预备孔的第五材料层，以在预备孔内限定第一气隙，并形成连接到预备孔的通孔 通过从与预备孔重叠的第五材料层穿透到第一堆叠结构。

公开(公告)号：US20160322382A1

公开(公告)日：2016-11-03

申请号：US14870164

申请日：2015-09-30

申请人： SK hynix Inc.

发明人： Sang Bum LEE

IPC分类号： H01L27/115 ,  H01L21/283 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/31116 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66825 ,  H01L29/66833

摘要： A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately stacked, forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers are alternately stacked, forming preliminary holes penetrating the second stack structure, forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside the preliminary holes, and forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary holes to the first stack structure.

摘要翻译： 一种制造半导体器件的方法包括在下部结构上形成第一堆叠结构，其中第一材料层和第二材料层交替堆叠，在第一堆叠结构上形成第二堆叠结构，其中第三层和第四层 材料层交替堆叠，形成穿过第二堆叠结构的初步孔，形成覆盖第二堆叠结构上的预备孔的第五材料层，以在预备孔内限定第一气隙，并形成连接到预备孔的通孔 通过从与预备孔重叠的第五材料层穿透到第一堆叠结构。

公开(公告)号：US09455267B2

公开(公告)日：2016-09-27

申请号：US14491315

申请日：2014-09-19

申请人： SANDISK TECHNOLOGIES INC.

发明人： Yanli Zhang ,  Johann Alsmeier

IPC分类号： H01L23/528 ,  H01L21/283 ,  H01L21/768 ,  H01L21/31 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234 ,  G11C16/06 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/06 ,  H01L21/02365 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/31 ,  H01L21/32133 ,  H01L21/768 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/0657 ,  H01L29/41775 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.

摘要翻译： 单片三维NAND串包括在至少一个有源区域中基本上平行于衬底的主表面延伸的多个控制栅电极，多个半导体沟道具有多个半导体沟道中的每一个的至少一个端部延伸 基本上垂直于衬底的主表面，位于多个控制栅电极中的每一个和多个半导体沟道中的每个相应半导体沟道之间的至少一个存储膜，以及至少一个基本上垂直于主体的第一狭缝沟槽 基板的表面。 多个控制栅极电极中的每一个具有与至少一个有源区域中的至少一个第一狭缝沟槽相邻的非线性侧壁。

公开(公告)号：US20160268387A1

公开(公告)日：2016-09-15

申请号：US14643558

申请日：2015-03-10

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Eng Huat TOH ,  Shyue Seng (Jason) TAN

IPC分类号： H01L29/423 ,  H01L29/10 ,  H01L29/788

CPC分类号： H01L29/42328 ,  H01L29/1033 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352

摘要： A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.

公开(公告)号：US20160155838A1

公开(公告)日：2016-06-02

申请号：US15006522

申请日：2016-01-26

申请人： Samsung Electronics Co., Ltd.

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.