公开(公告)号：US20190214404A1

公开(公告)日：2019-07-11

申请号：US16257357

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

公开(公告)号：US20190206888A1

公开(公告)日：2019-07-04

申请号：US15859499

申请日：2017-12-30

Applicant: Haibing Peng

Inventor： Haibing Peng

IPC: H01L27/11568 ,  H01L29/78 ,  H01L29/417 ,  H01L29/51 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L29/41791 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7883 ,  H01L29/792

Abstract: The present invention provides architectures of high-density NOR flash memory consisting of arrays of memory cells (i.e., field effect transistors) with uniquely designed sidewall charge-storage structures to solve the leakage problem typically associated with overerase in traditional NOR flash memory. This feature is particularly useful for applications such as embedded flash memory.

公开(公告)号：US20190198324A1

公开(公告)日：2019-06-27

申请号：US16292021

申请日：2019-03-04

Applicant: Micron Technology, Inc.

Inventor： Yushi Hu ,  Shu Qin

IPC: H01L21/225 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/2253 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

公开(公告)号：US20190013415A1

公开(公告)日：2019-01-10

申请号：US15641704

申请日：2017-07-05

Applicant: Micron Technology, Inc.

Inventor： Arup Bhattacharyya

IPC: H01L29/792 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  G11C17/12

CPC classification number: H01L29/7923 ,  G11C16/0475 ,  G11C16/16 ,  G11C17/123 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7926

Abstract: In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.

公开(公告)号：US20180308957A1

公开(公告)日：2018-10-25

申请号：US15898201

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L27/115 ,  G11C16/04

CPC classification number: H01L29/66833 ,  G11C16/0475 ,  H01L21/28194 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: An insulating film configuring an uppermost layer of a gate insulating film of a memory cell comprises a silicon oxide film and is a layer to which a metal or metal oxide is added. A formation step of the insulating film comprises the steps of: forming the silicon oxide film; and adding the metal or the metal oxide in an atomic or molecular state by a sputtering process onto the silicon oxide film. Oxide of the metal has a higher dielectric constant than silicon oxide, and the metal oxide has a higher dielectric constant than silicon oxide. A High-K added layer is thus used as the insulating film configuring the gate insulating film of the memory cell, thereby a high saturation level of a threshold voltage can be maintained while a drive voltage (applied voltage for erase or write) is reduced, leading to improvement in reliability of the memory cell.

公开(公告)号：US09997641B2

公开(公告)日：2018-06-12

申请号：US15051279

申请日：2016-02-23

Applicant: Cypress Semiconductor Corporation

Inventor： Fredrick B. Jenne ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/3143 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/515 ,  H01L29/518 ,  H01L29/66833

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

公开(公告)号：US09991274B2

公开(公告)日：2018-06-05

申请号：US15343591

申请日：2016-11-04

Applicant: Toshiba Memory Corporation

Inventor： Naoki Yasuda

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11565 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02326 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

公开(公告)号：US09985049B1

公开(公告)日：2018-05-29

申请号：US15581762

申请日：2017-04-28

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Richard J. Hill ,  John A. Smythe

IPC: H01L21/8238 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28282 ,  H01L29/1037 ,  H01L29/66545

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevationally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge-storage material by insulative charge-passage material. All of the charge-storage material of individual of the elevationally-extending strings of memory cells is laterally outward of all of the insulative charge-passage material of the individual elevationally-extending strings of memory cells. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US09985047B2

公开(公告)日：2018-05-29

申请号：US15188430

申请日：2016-06-21

Applicant: SK hynix Inc.

Inventor： Seung Cheol Lee

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L49/02

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L28/00

Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a multi-layered stack; forming a vertical hole in the stack; forming a plurality of material layers over a bottom and a sidewall of the vertical hole, wherein the plurality of material layers includes a first material layer and a second material layer, wherein the second material layer is provided under the first material layer; patterning the first material layer located over the bottom of the vertical hole to form a first opening, wherein the first opening exposes the second material layer; and patterning the second material layer exposed by the first opening using a difference in an etch rate between the first material layer and the second material layer.

公开(公告)号：US09985045B2

公开(公告)日：2018-05-29

申请号：US15837109

申请日：2017-12-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/1157 ,  H01L21/28 ,  H01L21/033 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11582 ,  H01L28/00

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.