公开(公告)号：US20240161826A1

公开(公告)日：2024-05-16

申请号：US18420874

申请日：2024-01-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Ming-Hsiu LEE

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/046 ,  G11C16/0475 ,  G11C2211/4016

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

公开(公告)号：US20230352101A1

公开(公告)日：2023-11-02

申请号：US18219083

申请日：2023-07-06

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/34 ,  H03M13/15

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G06F11/1068 ,  G11C29/52 ,  G06F11/1072 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/3427 ,  H03M13/152 ,  G11C2211/5644 ,  G11C2211/5648 ,  G11C16/0475

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US20190156889A1

公开(公告)日：2019-05-23

申请号：US16239456

申请日：2019-01-03

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  H01L27/105 ,  H01L29/78 ,  H01L27/115 ,  H01L27/108 ,  G11C11/56 ,  H01L29/792 ,  G11C16/04 ,  G11C16/02

CPC classification number: G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

公开(公告)号：US10073982B2

公开(公告)日：2018-09-11

申请号：US14909970

申请日：2013-08-15

Applicant: Renesas Electronics Corporation

Inventor： Seiji Sawada

IPC: G06F21/62 ,  G06F3/06 ,  G06F12/14 ,  G11C16/04 ,  G06F21/85 ,  G11C16/06

CPC classification number: G06F21/6218 ,  G06F3/0623 ,  G06F3/0638 ,  G06F3/0683 ,  G06F12/1408 ,  G06F21/85 ,  G11C7/1012 ,  G11C7/1087 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/06 ,  G11C16/3427

Abstract: A scramble unit subjects data to be written into twin cells in a first storage unit to scramble processing with the use of scramble data. A write unit writes write data subjected to the scramble processing into the twin cells in the first storage unit. A write unit writes scramble data into a memory cell in a second storage unit. A descramble unit subjects the data read from the first storage unit to descramble processing with the use of scramble data read from the second storage unit.

公开(公告)号：US09966141B2

公开(公告)日：2018-05-08

申请号：US15047759

申请日：2016-02-19

Applicant: NSCore, Inc.

Inventor： Tadahiko Horiuchi

IPC: G11C16/04 ,  G11C7/06 ,  G11C16/26 ,  H01L29/47 ,  H01L29/792 ,  H01L29/78 ,  H01L29/08 ,  G11C16/10

CPC classification number: G11C16/0466 ,  G11C7/06 ,  G11C7/065 ,  G11C11/418 ,  G11C11/419 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/26 ,  H01L28/00 ,  H01L29/0847 ,  H01L29/47 ,  H01L29/66492 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7839 ,  H01L29/792

Abstract: A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

公开(公告)号：US20180019134A1

公开(公告)日：2018-01-18

申请号：US15647692

申请日：2017-07-12

Applicant: SK hynix Inc. ,  SOGANG UNIVERSITY RESEARCH FOUNDATION

Inventor： Woo Young CHOI

IPC: H01L21/28 ,  H01L27/115 ,  H01L27/06 ,  H01L29/792 ,  G11C16/04

CPC classification number: H01L29/40117 ,  G11C16/0475 ,  G11C16/0483 ,  H01L21/28185 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792

Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer, a data storage layer disposed on the channel layer, a plurality of control gates arranged on the data storage layer and spaced apart from one another, and conductive cover layers disposed on sidewalls of the control gates facing each other. The plurality of control gates includes a first conductor having a first work function. The conductive cover layers include a second conductor having a second work function that is greater than the first work function.

公开(公告)号：US20170271018A1

公开(公告)日：2017-09-21

申请号：US15473439

申请日：2017-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kunio TANI

IPC: G11C16/14 ,  G11C16/22 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/105 ,  G11C16/107 ,  G11C16/22 ,  G11C16/28 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477

Abstract: When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.

公开(公告)号：US09715933B2

公开(公告)日：2017-07-25

申请号：US15136838

申请日：2016-04-22

Applicant: NEO Semiconductor, Inc.

Inventor： Fu-Chang Hsu

IPC: G11C16/04 ,  G11C16/10 ,  H01L29/792 ,  H01L27/12 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G11C7/10 ,  G11C11/401

CPC classification number: G11C16/0475 ,  G11C7/1015 ,  G11C11/401 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/28282 ,  H01L27/1211 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.

公开(公告)号：US20170154884A1

公开(公告)日：2017-06-01

申请号：US15429512

申请日：2017-02-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/06 ,  G11C16/04 ,  H01L29/792 ,  H01L27/11565 ,  H01L29/66 ,  H01L27/11568

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US09666294B2

公开(公告)日：2017-05-30

申请号：US15170952

申请日：2016-06-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/00 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.