公开(公告)号：US20250022508A1

公开(公告)日：2025-01-16

申请号：US18903041

申请日：2024-10-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE ,  Ming-Hsiu LEE

IPC: G11C13/00 ,  G06F7/544

Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

公开(公告)号：US20240371453A1

公开(公告)日：2024-11-07

申请号：US18312630

申请日：2023-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G11C17/18 ,  G06F7/544 ,  G11C17/16

Abstract: A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.

公开(公告)号：US20240311620A1

公开(公告)日：2024-09-19

申请号：US18185751

申请日：2023-03-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G06N3/0464

CPC classification number: G06N3/0464

Abstract: A neural network computing method and a neural network computing device are provided. The neural network computing method includes the following steps. At least one chosen layer is decided. A plurality of front layers previous to the chosen layer are decided. A selected element is selected from a plurality of chosen elements in the chosen layer. A front computing data group related to the selected element is defined. The front computing data group is composed of only part of a plurality of front elements in the front layers. The selected element is computed according to the at least one front computing data group.

公开(公告)号：US20240012567A1

公开(公告)日：2024-01-11

申请号：US18069255

申请日：2022-12-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Tian-Cih BO ,  Ming-Hsiu LEE

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory device is provided. The memory device includes channel layers, word lines, memory layers disposed between the channel layers and the word lines, and memory cells defined at cross-points of the channel layers and the word lines. The memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n. In the first operation, a first electric field is produced in a portion of the memory layers. The word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field.

公开(公告)号：US20230420047A1

公开(公告)日：2023-12-28

申请号：US17846304

申请日：2022-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Tian-Cih BO ,  Feng-Min LEE

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

公开(公告)号：US20230273737A1

公开(公告)日：2023-08-31

申请号：US17680388

申请日：2022-02-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu LIN ,  Feng-Min LEE

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0673

Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.

公开(公告)号：US20230045495A1

公开(公告)日：2023-02-09

申请号：US17392365

申请日：2021-08-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Erh-Kun LAI ,  Dai-Ying LEE ,  Yu-Hsuan LIN ,  Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

公开(公告)号：US20190244662A1

公开(公告)日：2019-08-08

申请号：US15887166

申请日：2018-02-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Yu-Yu LIN

IPC: G11C13/00 ,  G06F7/544 ,  G11C16/04

CPC classification number: G11C11/54 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/2436

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

公开(公告)号：US20240365565A1

公开(公告)日：2024-10-31

申请号：US18306289

申请日：2023-04-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun LAI ,  Feng-Min LEE

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/34 ,  H10B61/22 ,  H10B63/845

Abstract: A memory device and a method for manufacturing the same are provided. The memory device includes drain pillar structures, source pillar structures, memory structures surrounding the drain pillar structures respectively, a channel structure, and a gate structure surrounding the drain pillar structures, the source pillar structures and the channel structure. The channel structure is divided into arc channel parts by the drain pillar structures and the source pillar structures.

公开(公告)号：US20240363164A1

公开(公告)日：2024-10-31

申请号：US18765452

申请日：2024-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Ming-Hsiu Lee

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.