公开(公告)号：US20240071821A1

公开(公告)日：2024-02-29

申请号：US17821479

申请日：2022-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Yu-Chao HUANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266

Abstract: A semiconductor element and a method for manufacturing the same are provided. The semiconductor element includes a plug and a via on the plug and electrically connected to the plug. The plug includes a tungsten plug and a conductive layer on the tungsten plug. The tungsten plug and the conductive layer include different materials. The tungsten plug has a first width in a lateral direction. The conductive layer has a second width in the lateral direction. The second width is greater than or equal to the first width. The conductive layer is between the via and the tungsten plug.

公开(公告)号：US20230079160A1

公开(公告)日：2023-03-16

申请号：US17475439

申请日：2021-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien LU ,  Yun-Yuan WANG ,  Dai-Ying LEE

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

公开(公告)号：US20240304579A1

公开(公告)日：2024-09-12

申请号：US18178580

申请日：2023-03-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Cheng-Hsien LU

IPC: H01L23/00 ,  H10B80/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/48 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/03848 ,  H01L2224/05649 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/08112 ,  H01L2224/08146 ,  H01L2224/48221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443

Abstract: Semiconductor devices and a method for forming a semiconductor device are provided. The semiconductor device includes a substrate, a first semiconductor structure on the substrate, a second semiconductor structure on the first semiconductor structure, and a wire coupled between the substrate and the first semiconductor structure. The first semiconductor structure and the second semiconductor structure are electrically connected to the substrate through the wire. A footprint of the first semiconductor structure is greater than a footprint of the second semiconductor structure.

公开(公告)号：US20240203858A1

公开(公告)日：2024-06-20

申请号：US18594046

申请日：2024-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien LU ,  Yun-Yuan WANG ,  Dai-Ying LEE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49866 ,  H01L23/49877

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

公开(公告)号：US20220284952A1

公开(公告)日：2022-09-08

申请号：US17191944

申请日：2021-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan WANG ,  Dai-Ying LEE

IPC: G11C13/00 ,  H03K19/20

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array including a plurality of memory cells; a plurality of bit lines coupled to the memory array; a plurality of word lines coupled to the memory array; and a plurality of conductance controllable units coupled to the memory array; wherein a memory cell group and at least one conductance controllable unit among the conductance controllable units form a logic operation unit, and a logic operation function of the logic operation unit is determined by an equivalent conductance of the at least one conductance controllable unit.

公开(公告)号：US20240242767A1

公开(公告)日：2024-07-18

申请号：US18623116

申请日：2024-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Dai-Ying LEE ,  Ming-Hsiu LEE

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/40

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/40 ,  G11C2029/4002

Abstract: A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

公开(公告)号：US20230378053A1

公开(公告)日：2023-11-23

申请号：US17748111

申请日：2022-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien LU ,  Yun-Yuan WANG ,  Ming-Hsiu LEE ,  Dai-Ying LEE

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/5329 ,  H01L23/53276 ,  H01L23/53209

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

公开(公告)号：US20220199490A1

公开(公告)日：2022-06-23

申请号：US17688961

申请日：2022-03-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Ming-Hsiu LEE

IPC: H01L23/40 ,  H01L21/48 ,  H01L21/768

Abstract: A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size.

公开(公告)号：US20200227414A1

公开(公告)日：2020-07-16

申请号：US16249049

申请日：2019-01-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-Hung WANG ,  Yu-Hsuan LIN ,  Dai-Ying LEE

IPC: H01L27/105

Abstract: A semiconductor structure includes a memory array. The memory array has a plurality of memory units. The memory units include a first memory unit and a second memory unit. The first memory unit has a first resistance. The second memory unit has a second resistance. Both of the first resistance and the second resistance are in a range of 105Ω to 109Ω, and the second resistance is larger than the first resistance.

公开(公告)号：US20240090238A1

公开(公告)日：2024-03-14

申请号：US18519230

申请日：2023-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Erh-Kun LAI ,  Dai-Ying LEE ,  Yu-Hsuan LIN ,  Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/845 ,  H10B61/22 ,  H10B63/34 ,  H10N50/01 ,  H10N70/066

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.