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    OPERATING METHOD FOR SEMICONDUCTOR CIRCUIT
    3.
    发明申请
    OPERATING METHOD FOR SEMICONDUCTOR CIRCUIT 有权

    公开(公告)号：US20210193201A1

    公开(公告)日：2021-06-24

    申请号：US17195712

    申请日：2021-03-09

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan LIN ,  Chao-Hung WANG

    IPC: G11C7/22 ,  G06F3/06

    Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

    METHOD FOR OPERATING MEMORY DEVICE AND MEMORY DEVICE
    4.
    发明公开
    METHOD FOR OPERATING MEMORY DEVICE AND MEMORY DEVICE 审中-公开

    公开(公告)号：US20240184464A1

    公开(公告)日：2024-06-06

    申请号：US18302942

    申请日：2023-04-19

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan LIN ,  Hsiang-Lan LUNG ,  Cheng-Lin SUNG

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A method for operating a memory device is provided. The method includes following steps. First, a priority of a refresh operation and a priority of an inference operation for at least a portion of a memory array of the memory device are determined. The refresh operation and the inference operation are performed according to a determination result of the priority of the refresh operation and the priority of the inference operation. If the priority of the refresh operation is lower than the priority of inference operation, perform the inference operation in the at least a portion, and perform the refresh operation after performing the inference operation. If the priority of the refresh operation is higher than the priority of inference operation, perform the refresh operation in the at least a portion, and perform the inference operation after performing the refresh operation.

    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    5.
    发明申请
    MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20230045495A1

    公开(公告)日：2023-02-09

    申请号：US17392365

    申请日：2021-08-03

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Feng-Min LEE ,  Erh-Kun LAI ,  Dai-Ying LEE ,  Yu-Hsuan LIN ,  Po-Hao TSENG ,  Ming-Hsiu LEE

    IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00

    Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

    STORAGE DEVICE FOR GENERATING IDENTITY CODE AND IDENTITY CODE GENERATING METHOD
    6.
    发明申请
    STORAGE DEVICE FOR GENERATING IDENTITY CODE AND IDENTITY CODE GENERATING METHOD 有权

    公开(公告)号：US20220359016A1

    公开(公告)日：2022-11-10

    申请号：US17388079

    申请日：2021-07-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan LIN ,  Dai-Ying LEE ,  Ming-Hsiu LEE

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/40

    Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

    INPUT MAPPING TO REDUCE NON-IDEAL EFFECT OF COMPUTE-IN-MEMORY
    7.
    发明申请
    INPUT MAPPING TO REDUCE NON-IDEAL EFFECT OF COMPUTE-IN-MEMORY 有权

    公开(公告)号：US20220012586A1

    公开(公告)日：2022-01-13

    申请号：US17079341

    申请日：2020-10-23

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan LIN ,  Po-Kai HSU ,  Dai-Ying LEE

    IPC: G06N3/08 ,  G06N5/04

    Abstract: An inference engine for a neural network uses a compute-in-memory array storing a kernel coefficients. A clamped input matrix is provided to the compute-in-memory array to produce an output vector representing a function of the clamped input vector and the kernel. A circuit is included receiving an input vector, where elements of the input vector have values in a first range of values. The circuit clamps the values of the elements of the input vector a limit of a second range of values to provide the clamped input vector. The second range of values is more narrow than the first range of values, and set according to the characteristics of the compute-in-memory array. The first range of values can be used in training using digital computation resources, and the second range of values can be used in inference using the compute-in-memory array.

    MEMORY DEVICE AND OPERATION METHOD THEREOF
    8.
    发明申请
    MEMORY DEVICE AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20200349428A1

    公开(公告)日：2020-11-05

    申请号：US16522986

    申请日：2019-07-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chao-Hung WANG ,  Yu-Hsuan LIN ,  Ming-Liang WEI ,  Dai-Ying LEE

    IPC: G06N3/08 ,  G06F3/06

    Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.

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