公开(公告)号：US20230034366A1

公开(公告)日：2023-02-02

申请号：US17388053

申请日：2021-07-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Po-Kai HSU ,  Ming-Liang WEI

IPC: G06N3/08

Abstract: The present invention discloses a memory and a training method for neutral network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neutral network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neutral network; and programming the memory according to the weights.

公开(公告)号：US20230033998A1

公开(公告)日：2023-02-02

申请号：US17539257

申请日：2021-12-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Bo-Rong LIN ,  Ming-Liang WEI ,  Hsiang-Pang LI ,  Nai-Jia DONG ,  Hsiang-Yun CHENG ,  Chia-Lin YANG

IPC: G06F12/0804

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

公开(公告)号：US20230118468A1

公开(公告)日：2023-04-20

申请号：US17502067

申请日：2021-10-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan WANG ,  Ming-Liang WEI ,  Ming-Hsiu LEE ,  Cheng-Hsien LU

IPC: G06F7/575 ,  G11C16/26

Abstract: A memory device and a computing method thereof are provided in the present disclosure. The computing method includes the following steps. A plurality of input-values of a model computation are respectively received through a plurality of first-word-lines of a memory array. Inverted logic values of the input-values are respectively received through a plurality of second-word-lines. The input-values are respectively received through a plurality of first-bit-lines. The inverted logic values are respectively received through a plurality of second-bit-lines. Logic XNOR operation is performed according to each of the input-values and each of the inverted values to obtain a first computation result, and multiplied with one of self-coefficients or one of mutual coefficients of the model computation to obtain a plurality of output-values. The output-values are outputted through a plurality of common-source-lines.

公开(公告)号：US20240355390A1

公开(公告)日：2024-10-24

申请号：US18595672

申请日：2024-03-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Liang WEI ,  Hsiang-Pang LI ,  You-Kai ZHENG ,  Chia-Lin YANG

IPC: G11C13/02 ,  G16B30/10 ,  G16B50/30

CPC classification number: G11C13/02 ,  G16B30/10 ,  G16B50/30

Abstract: A storage system capable of executing data processing, includes the following elements. A first control unit of a storage device, for cooperating with a sequencer to perform a clustering process on a plurality of original sequences to obtain a plurality of read sequences, generating a plurality of read binary vectors corresponding to the read sequences, and generating a pruned filtering binary vector according to a reference sequence. A first storage module of the storage device, for storing the read binary vectors and the pruned filtering binary vector, and executing an in-memory computing (IMC) according to the read binary vectors and the pruned filtering binary vector, so as to generate a filtered cluster read set. A processing device, for executing an aligning process according to the filtered cluster read set and the reference sequence.

公开(公告)号：US20200349428A1

公开(公告)日：2020-11-05

申请号：US16522986

申请日：2019-07-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-Hung WANG ,  Yu-Hsuan LIN ,  Ming-Liang WEI ,  Dai-Ying LEE

IPC: G06N3/08 ,  G06F3/06

Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.