公开(公告)号：US20200027488A1

公开(公告)日：2020-01-23

申请号：US16154831

申请日：2018-10-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Chao-Hung WANG

IPC: G11C7/22 ,  G06F3/06

Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

公开(公告)号：US20200227414A1

公开(公告)日：2020-07-16

申请号：US16249049

申请日：2019-01-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-Hung WANG ,  Yu-Hsuan LIN ,  Dai-Ying LEE

IPC: H01L27/105

Abstract: A semiconductor structure includes a memory array. The memory array has a plurality of memory units. The memory units include a first memory unit and a second memory unit. The first memory unit has a first resistance. The second memory unit has a second resistance. Both of the first resistance and the second resistance are in a range of 105Ω to 109Ω, and the second resistance is larger than the first resistance.

公开(公告)号：US20210193201A1

公开(公告)日：2021-06-24

申请号：US17195712

申请日：2021-03-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Chao-Hung WANG

IPC: G11C7/22 ,  G06F3/06

Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

公开(公告)号：US20200349428A1

公开(公告)日：2020-11-05

申请号：US16522986

申请日：2019-07-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-Hung WANG ,  Yu-Hsuan LIN ,  Ming-Liang WEI ,  Dai-Ying LEE

IPC: G06N3/08 ,  G06F3/06

Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.

公开(公告)号：US20200058859A1

公开(公告)日：2020-02-20

申请号：US16102985

申请日：2018-08-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chao-Hung WANG ,  Dai-Ying LEE ,  Kuang-Hao CHIANG ,  Yu-Hsuan LIN ,  Tsung-Ming CHEN

IPC: H01L45/00

Abstract: A resistive memory device includes a first electrode, a resistance switching layer and a second electrode. The resistance switching layer is disposed on the first electrode and includes a ternary transition metal oxide. The second electrode is disposed on the resistance switching layer.