公开(公告)号：US20240363764A1

公开(公告)日：2024-10-31

申请号：US18768737

申请日：2024-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyongsik Yeom ,  Youngcheon Jeong ,  Yongkyu Lee

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H10B41/35 ,  H10B41/41

CPC classification number: H01L29/788 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/6656 ,  H01L29/66825 ,  H10B41/35 ,  H10B41/41

Abstract: An integrated circuit includes: a source region, split gate structures on opposing sides of the source region, the split gate structures including a floating gate electrode layer and a control gate electrode layer, an erase gate structure between the split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures on outer sidewalls of the split gate structures, and a pair of gate spacers. Each gate spacer is disposed between one of the split gate structures and one of the selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, and is further disposed on an outer side wall of the one of the split gate structures. A lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.

公开(公告)号：US20240355936A1

公开(公告)日：2024-10-24

申请号：US18327081

申请日：2023-06-01

Applicant: United Microelectronics Corp.

Inventor： Boon Keat Toh ,  Chih-Hsin Chang ,  Szu Han Wu ,  Chi Ren

IPC: H01L29/788 ,  H01L29/45 ,  H01L29/66 ,  H10B41/35

CPC classification number: H01L29/788 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66825 ,  H10B41/35

Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate having a first memory region. The first memory region includes a first dielectric layer, a first floating gate, a first inter-gate dielectric layer, a control gate and a first contact. The first dielectric layer is disposed on the substrate. The first floating gate is disposed on the first dielectric layer. The first inter-gate dielectric layer is disposed on the first floating layer. The control gate is disposed on the first inter-gate dielectric layer. The first contact penetrates through the first control gate and the first inter-gate dielectric layer and is landed on the first floating gate.

公开(公告)号：US20240347612A1

公开(公告)日：2024-10-17

申请号：US18751382

申请日：2024-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SZU-YU WANG ,  CHIA-WEI HU

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/40114 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66545

Abstract: A semiconductor structure for a memory device is provided. The semiconductor structure includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer. The first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration. The second gate structure includes a p-type gate structure, and second dopant concentration of the second layer is greater than the first dopant concentration of the first layer.

公开(公告)号：US20240315017A1

公开(公告)日：2024-09-19

申请号：US18135712

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEICHANG LIU ,  Wang Xiang ,  CHIA CHING HSU ,  Yung-Lin Tseng ,  Shen-De Wang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L28/20 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.

公开(公告)号：US20240304693A1

公开(公告)日：2024-09-12

申请号：US18667449

申请日：2024-05-17

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Hang YIN ,  Zhipeng WU ,  Kai HAN ,  Lu ZHANG ,  Pan WANG ,  Xiangning WANG ,  Hui ZHANG ,  Jingjing GENG ,  Meng XIAO

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/42352 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.

公开(公告)号：US20240284667A1

公开(公告)日：2024-08-22

申请号：US18649949

申请日：2024-04-29

Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： CHUNG-YI CHEN

IPC: H10B41/27 ,  H01L25/07 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/27 ,  H01L25/074 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

公开(公告)号：US12068313B2

公开(公告)日：2024-08-20

申请号：US16995538

申请日：2020-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ming Chyi Liu

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30 ,  H01L29/6656

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arrangement includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

公开(公告)号：US12068187B2

公开(公告)日：2024-08-20

申请号：US18424790

申请日：2024-01-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US12057481B2

公开(公告)日：2024-08-06

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Xiaojuan Gao ,  Chi Ren

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US12046649B2

公开(公告)日：2024-07-23

申请号：US17810814

申请日：2022-07-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Szu-Yu Wang ,  Chia-Wei Hu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/40114 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66545

Abstract: A method for forming a semiconductor structure includes receiving a substrate including a first gate structure; forming a first semiconductor layer over the first gate structure, forming a second semiconductor layer on the first semiconductor layer, performing an etching back operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer with an etchant, the etching rate of the first semiconductor layer upon exposure to the etchant is greater than an etching rate of the second semiconductor layer upon exposure to the etchant; forming a hard mask spacer over the first semiconductor layer and the second semiconductor layer, a portion of the second semiconductor layer is exposed through the hard mask spacer; removing the portions of the second semiconductor layer and the first semiconductor layer through the hard mask spacer to form a second gate structure and expose a portion of the substrate.