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公开(公告)号：US20240363385A1
公开(公告)日：2024-10-31
申请号：US18736423
申请日：2024-06-06
Applicant: Monolithic 3D Inc.
Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC: H01L21/683 , G11C8/16 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/00 , H01L23/367 , H01L23/48 , H01L23/525 , H01L25/00 , H01L25/065 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , H10B10/00 , H10B12/00 , H10B20/00 , H10B20/20 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40
CPC classification number: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H10B10/00 , H10B10/125 , H10B12/053 , H10B12/09 , H10B12/20 , H10B12/50 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/3677 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/1214 , H01L27/1266 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H10B12/05 , H10B20/20
Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
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公开(公告)号：US12120943B2
公开(公告)日：2024-10-15
申请号：US18363944
申请日：2023-08-02
Applicant: Samsung Display Co., LTD.
Inventor： Wang Woo Lee , Sung Ho Kim , Hyeon Sik Kim , Joon Hyoung Park , Seok Je Seong , Jin Sung An , Jin Seok Oh , Min Woo Woo , Ji Seon Lee , Pil Suk Lee , Yun Sik Joo
IPC: H10K59/131 , H10K59/121 , H10K71/00 , H10K71/80 , H10K77/10 , H01L27/12 , H01L29/66 , H01L29/786 , H10K59/12 , H10K102/00
CPC classification number: H10K77/111 , H10K59/1213 , H10K59/131 , H10K71/00 , H10K71/80 , H01L27/1218 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/1266 , H01L27/127 , H01L27/1288 , H01L29/66757 , H01L29/66969 , H01L29/78675 , H01L29/7869 , H10K59/1201 , H10K2102/311
Abstract: A display device includes a supporting substrate including a polymeric material, base substrate disposed on an upper surface of the supporting substrate, a pixel array disposed in a display area of the base substrate, a transfer wiring disposed in a bending area of the base substrate and electrically connected to the pixel array, and an organic filling portion disposed under the transfer wiring in the bending area. The base substrate includes an organic film including a polymeric material, and an inorganic barrier film overlapping the organic film and extending outwardly from an edge of the organic film. The organic filling portion contacts the organic film of the base substrate.
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公开(公告)号：US20240321904A1
公开(公告)日：2024-09-26
申请号：US18732591
申请日：2024-06-03
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Jihyun KIM , Taewook KANG , Byungsoo SO , Hyuneok SHIN , Wooseok JEON
IPC: H01L27/12 , H01L23/00 , H01L25/16 , H01L27/15 , H10K59/131
CPC classification number: H01L27/124 , H01L24/05 , H01L27/1218 , H01L27/1266 , H01L24/08 , H01L24/32 , H01L24/80 , H01L24/83 , H01L25/167 , H01L27/156 , H01L2224/05541 , H01L2224/05571 , H01L2224/08225 , H01L2224/32225 , H01L2224/80203 , H01L2224/80801 , H01L2224/83203 , H01L2224/83851 , H10K59/131
Abstract: A display device including a display area and a non-display area further includes a base layer including a first surface and a second surface opposite to the first surface, the base layer having, in the non-display area, an opening portion penetrating the first surface and the second surface; a pad unit including a terminal on the first surface, the pad unit extending from the first surface to the opening portion; a connection line connected to the terminal on the first surface, the connection line extending from the non-display area to the display area; an insulating layer covering the terminal and the connection line; a thin-film transistor including a semiconductor layer on the insulating layer, the thin-film transistor being connected to the connection line; and a display element connected to the thin-film transistor, the display element being in the display area.
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公开(公告)号：US12080685B2
公开(公告)日：2024-09-03
申请号：US17083403
申请日：2020-10-29
Applicant: VueReal Inc.
Inventor： Gholamreza Chaji , Ehsanollah Fathi
IPC: H01L25/075 , H01L21/683 , H01L27/12 , H01L33/62
CPC classification number: H01L25/0753 , H01L21/6835 , H01L27/1214 , H01L27/1266 , H01L33/62 , H01L2221/68322 , H01L2221/68354 , H01L2221/68363 , H01L2221/68381 , H01L2933/0066
Abstract: In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The microdevices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.
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公开(公告)号：US12048207B2
公开(公告)日：2024-07-23
申请号：US18138866
申请日：2023-04-25
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Shunpei Yamazaki , Masakatsu Ohno , Hiroki Adachi , Satoru Idojiri , Koichi Takeshima
IPC: H01L23/00 , B23K26/04 , B23K26/06 , B23K26/0622 , B23K26/08 , H01L27/12 , H01L29/24 , H01L29/66 , H01L29/786 , H10K50/842 , H10K50/844 , H10K59/121 , H10K59/124 , H10K59/126 , H10K59/38 , H10K71/00 , H10K71/40 , H10K71/50 , H10K71/80 , H10K77/10 , H10K50/18 , H10K50/86 , H10K59/12 , H10K102/00 , H10N30/074
CPC classification number: H10K59/126 , B23K26/04 , B23K26/0617 , B23K26/0622 , B23K26/0643 , B23K26/0648 , B23K26/083 , H01L27/1225 , H01L27/1266 , H01L29/24 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H10K50/8426 , H10K50/844 , H10K59/1213 , H10K59/124 , H10K59/38 , H10K71/00 , H10K71/421 , H10K71/50 , H10K71/80 , H10K77/111 , H10K50/18 , H10K50/865 , H10K59/12 , H10K59/1201 , H10K2102/311 , H10K2102/351 , H10N30/074 , Y02E10/549 , Y02P70/50
Abstract: A first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer.
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公开(公告)号：US20240213073A1
公开(公告)日：2024-06-27
申请号：US18424790
申请日：2024-01-27
Applicant: Monolithic 3D Inc.
Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC: H01L21/683 , G11C8/16 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/00 , H01L23/367 , H01L23/48 , H01L23/525 , H01L25/00 , H01L25/065 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , H10B10/00 , H10B12/00 , H10B20/00 , H10B20/20 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40
CPC classification number: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H10B10/00 , H10B10/125 , H10B12/053 , H10B12/09 , H10B12/20 , H10B12/50 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/3677 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/1214 , H01L27/1266 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H10B12/05 , H10B20/20
Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
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公开(公告)号：US20240194691A1
公开(公告)日：2024-06-13
申请号：US18064954
申请日：2022-12-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ruilong Xie , Tao Li , Nicholas Alexander POLOMOFF , Chih-Chao Yang
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1266 , H01L27/1251
Abstract: A first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact. Forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, where the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.
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公开(公告)号：US11990484B2
公开(公告)日：2024-05-21
申请号：US17874875
申请日：2022-07-27
Applicant: PRAGMATIC PRINTING LTD.
Inventor： Richard Price , Brian Cobb , Neil Davies
CPC classification number: H01L27/1262 , H01L21/78 , H01L27/1218 , H01L27/1266
Abstract: The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
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公开(公告)号：US11935933B2
公开(公告)日：2024-03-19
申请号：US18131336
申请日：2023-04-05
Applicant: Intel Corporation
Inventor： Patrick Morrow , Rishabh Mehandru , Aaron D. Lilak , Kimin Jun
IPC: H01L27/12 , H01L21/8234 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/225 , H01L21/265
CPC classification number: H01L29/41791 , H01L21/823431 , H01L27/1266 , H01L29/0847 , H01L29/401 , H01L29/4236 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/66803 , H01L29/78 , H01L29/785 , H01L21/2254 , H01L21/26513 , H01L29/66545
Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
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公开(公告)号：US11881489B2
公开(公告)日：2024-01-23
申请号：US17991893
申请日：2022-11-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hisao Ikeda , Kouhei Toyotaka , Hideaki Shishido , Hiroyuki Miyake , Kohei Yokoyama , Yasuhiro Jinbo , Yoshitaka Dozen , Takaaki Nagata , Shinichi Hirasa
IPC: H01L27/02 , H10K59/35 , G09G3/20 , G09G3/3233 , H01L27/12 , H01L29/786 , H10K59/131 , G09G3/36 , G09G5/391
CPC classification number: H01L27/124 , G09G3/2003 , G09G3/3233 , H01L27/1225 , H01L27/1266 , H01L29/78648 , H10K59/131 , H10K59/352 , H10K59/353 , G09G3/3648 , G09G5/391 , G09G2300/0426 , G09G2300/0443 , G09G2300/0452 , G09G2300/0465 , G09G2300/0809 , G09G2300/0842 , G09G2320/0295 , G09G2320/043 , G09G2320/0693
Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
