公开(公告)号：US20240363514A1

公开(公告)日：2024-10-31

申请号：US18646659

申请日：2024-04-25

申请人： QUALCOMM Incorporated

发明人： Aniket PATIL ,  Hong Bok WE ,  Joan Rey Villarba BUOT

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L24/17 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81815

摘要： A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

公开(公告)号：US20240363508A1

公开(公告)日：2024-10-31

申请号：US18582880

申请日：2024-02-21

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hiroyuki NOGAWA

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/49811 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49838 ,  H01L25/0655

摘要： A semiconductor module includes: a semiconductor element; a housing for housing the semiconductor element, the housing including a terminal hole; a terminal in the terminal hole and being electrically connected to the semiconductor element; a holding member bonded by an adhesive to the housing; and a potting material in the housing, in which the terminal includes a plate-shaped leg between the holding member and the housing including a recess for accommodating the leg, the recess has a depth greater than a thickness of the leg, in the recess, a portion of the leg in a direction of length of the leg is provided with a passage for the adhesive, the passage being across the leg in a direction of thickness of the leg, and a width of the passage is greater than a difference between the depth of the recess and the thickness of the leg.

公开(公告)号：US12132008B2

公开(公告)日：2024-10-29

申请号：US17813357

申请日：2022-07-19

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/32 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/31 ,  H01L23/32 ,  H01L25/0655

摘要： Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

公开(公告)号：US12132005B2

公开(公告)日：2024-10-29

申请号：US18507176

申请日：2023-11-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/544 ,  H01L23/14 ,  H01L23/32 ,  H01L25/065

CPC分类号： H01L23/544 ,  H01L23/145 ,  H01L23/32 ,  H01L25/0655

摘要： Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.

公开(公告)号：US20240355774A1

公开(公告)日：2024-10-24

申请号：US18683482

申请日：2021-11-18

申请人： Mitsubishi Electric Corporation

发明人： Nozomi SAITO ,  Yuki YANO

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/40 ,  H01L23/3171 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L24/84 ,  H01L25/0655 ,  H01L2224/32225 ,  H01L2224/40155 ,  H01L2224/40475 ,  H01L2224/48155 ,  H01L2224/73263 ,  H01L2224/84007

摘要： The object is to provide a technology for enabling reduction of adhesion of a bonding material to a particular electrode. A semiconductor device includes: a semiconductor element with a surface including a first electrode and a second electrode; a protective film formed on the surface of the semiconductor element and having insulating properties, the protective film exposing the first electrode and the second electrode; a metal lead electrode bonded to the first electrode exposed from the protective film; and a bonding material with which the first electrode exposed from the protective film is bonded to the metal lead electrode. The metal lead electrode includes an abutment portion being a protrusion abutting the protective film and blocking between the bonding material and the second electrode in a cross-sectional view.

公开(公告)号：US12125804B2

公开(公告)日：2024-10-22

申请号：US18362989

申请日：2023-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Kang Hsieh ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Shih-Wei Chen

IPC分类号： H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/40 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/4006 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/50 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2221/68372 ,  H01L2224/95001 ,  H01L2924/3511

摘要： A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.

公开(公告)号：US20240347507A1

公开(公告)日：2024-10-17

申请号：US18444783

申请日：2024-02-19

申请人： Samsung Display Co., Ltd.

发明人： Hyun Min CHO ,  Jun Ho SIM ,  Jae Hun LEE ,  Yun Jong YEO ,  DAWOON JUNG ,  Yang-Ho JUNG ,  Yu-Gwang JEONG

IPC分类号： H01L25/065 ,  B60K35/22 ,  H01L27/12 ,  H01L33/58

CPC分类号： H01L25/0655 ,  B60K35/22 ,  H01L25/0652 ,  H01L27/124 ,  H01L33/58 ,  B60K2360/332 ,  B60K2360/343

摘要： A light emitting display device and a car including the same according to embodiments include: a substrate; a plurality of light emitting diodes that are disposed above the substrate and include a plurality of light emitting layers; a pixel defining layer that has openings corresponding to the plurality of light emitting layers; and a plurality of light blocking patterns that are disposed on the pixel defining layer and the plurality of light emitting layers, and extend in a first direction. Each of the plurality of light blocking patterns includes a first portion and a second portion formed on the first portion and having a width decreasing toward an upper portion thereof.

公开(公告)号：US20240347457A1

公开(公告)日：2024-10-17

申请号：US18750571

申请日：2024-06-21

申请人： Intel Corporation

发明人： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

摘要： Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US20240347402A1

公开(公告)日：2024-10-17

申请号：US18756679

申请日：2024-06-27

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Leonel Arana ,  Benjamin Duong

IPC分类号： H01L23/13 ,  H01L23/15 ,  H01L25/065

CPC分类号： H01L23/13 ,  H01L23/15 ,  H01L25/0655

摘要： Methods and apparatus to reduce delamination in hybrid cores are disclosed. An example hybrid core of an integrated circuit (IC) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.

公开(公告)号：US20240347348A1

公开(公告)日：2024-10-17

申请号：US18427834

申请日：2024-01-31

申请人： Powertech Technology Inc.

发明人： Shang-Yu Chang Chien

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L21/486 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49827 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a redistributed circuit structure, a plurality of chips, a second encapsulant, a plurality of supporting members, a first encapsulant, and a plurality of connection terminals is provided. The redistributed circuit structure has a first surface and a second surface opposite to each other. The chips are disposed on the second surface of the redistributed circuit structure. The second encapsulant is disposed on the second surface of the redistributed circuit structure and covers the chips. The supporting members are disposed on the first surface of the redistributed circuit structure. The first encapsulant is disposed on the first surface of the redistributed circuit structure and covers the supporting members. The connection terminals are connected to the supporting members.