公开(公告)号：US20240363575A1

公开(公告)日：2024-10-31

申请号：US18480897

申请日：2023-10-04

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jihwan KIM ,  Seungwon IM ,  Oseob JEON ,  Hangil SHIN ,  Taekyun KIM

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L24/24 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/82 ,  H01L25/072 ,  H01L25/115 ,  H01L23/4924 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A fan out package may include a plurality of semiconductor dies, each of the semiconductor dies including a first surface and a second surface opposite to the first surface. The fan out package includes a redistribution layer coupled to the first surface of each of the plurality of semiconductor dies, a dieback conductive member coupled to the second surface of each of the plurality of semiconductors dies, and an encapsulation material coupled to the plurality of semiconductor dies and the dieback conductive member.

公开(公告)号：US20240363470A1

公开(公告)日：2024-10-31

申请号：US18765853

申请日：2024-07-08

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Yeong Beom Ko ,  Dong Jin Kim ,  Se Woong Cha

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/3185 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/18162

摘要： A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

公开(公告)号：US20240363365A1

公开(公告)日：2024-10-31

申请号：US18769434

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US12132036B2

公开(公告)日：2024-10-29

申请号：US17478832

申请日：2021-09-17

申请人： SJ SEMICONDUCTOR (JIANGYIN) CORPORATION

发明人： Hanlung Tsai ,  Xingtao Xue ,  Chengchung Lin

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L33/54 ,  H01L33/62

CPC分类号： H01L25/167 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/211 ,  H01L2224/24147 ,  H01L2224/73209 ,  H01L2224/82005 ,  H01L2933/005 ,  H01L2933/0066

摘要： The present disclosure provides fan-out LED packaging structures and methods. The fan-out LED packaging structure at least comprises: an LED wafer, a packaging layer, a first redistribution layer, an IC control chip module, and a second redistribution layer. The LED wafer and the IC control chip module use metal wires of the first and second redistribution layers and metal-plated holes of the packaging layer to lead out and to control the LED wafer and the IC control chip. The present disclosure also provides fan-out LED packaging methods. The methods adopt metal plating in place of wire bonding, and adopt PI dielectric layers and rewiring layers in place of a base substrate, thus effectively reducing the LED package size.

公开(公告)号：US20240355697A1

公开(公告)日：2024-10-24

申请号：US18762478

申请日：2024-07-02

申请人： Intel Corporation

发明人： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

摘要： A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US12125804B2

公开(公告)日：2024-10-22

申请号：US18362989

申请日：2023-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Kang Hsieh ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Shih-Wei Chen

IPC分类号： H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/40 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/4006 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/50 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2221/68372 ,  H01L2224/95001 ,  H01L2924/3511

摘要： A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.

公开(公告)号：US20240332268A1

公开(公告)日：2024-10-03

申请号：US18739690

申请日：2024-06-11

申请人： Samsung Electronics Co., Ltd.

发明人： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

摘要： A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20240297146A1

公开(公告)日：2024-09-05

申请号：US18589254

申请日：2024-02-27

申请人： Kioxia Corporation

发明人： Shota KONUMA ,  Hiroshi FUJITA ,  Hisashi KATO ,  Naomi YANAI

IPC分类号： H01L23/00 ,  H01L21/265 ,  H01L21/324 ,  H10B80/00

CPC分类号： H01L24/96 ,  H01L21/2652 ,  H01L21/324 ,  H10B80/00 ,  H01L2224/96

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming, on a substrate, an active layer in which a dopant is implanted; forming a porous layer by making the active layer porous by an anodization treatment; forming a device layer including at least a part of a configuration of the semiconductor device above the porous layer; and cleaving the porous layer to remove the substrate.

公开(公告)号：US12068283B2

公开(公告)日：2024-08-20

申请号：US17502287

申请日：2021-10-15

申请人： Intel Corporation

发明人： Min-Tih Ted Lai ,  Florence R. Pon ,  Yuhong Cai ,  John G. Meyers

IPC分类号： H01L25/065 ,  H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L24/96 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/46 ,  H01L2224/4801 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00

摘要： An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

公开(公告)号：US12062603B2

公开(公告)日：2024-08-13

申请号：US18079555

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo

IPC分类号： H01L23/498 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482

CPC分类号： H01L23/49827 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L21/28568 ,  H01L23/49866 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/95001 ,  H01L2924/35121

摘要： Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.