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    MOLDED POWER MODULES
    5.
    发明公开
    MOLDED POWER MODULES 审中-公开

    公开(公告)号：US20230361011A1

    公开(公告)日：2023-11-09

    申请号：US18308467

    申请日：2023-04-27

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Seungwon IM ,  Oseob JEON

    IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/433

    CPC分类号： H01L23/49811 ,  H01L23/3121 ,  H01L23/4334

    摘要： In a general aspect, an electronic device assembly includes a substrate having a surface, a patterned metal layer disposed on the surface of the substrate, a semiconductor device circuit implemented on the patterned metal layer, and a molded body including a plurality of signal pin. A signal pin of the plurality of signal pins includes a first portion extending out of a first surface of the molded body. The first portion is externally accessible. The signal pin of the plurality of signal pins also includes a second portion extending out of a second surface of the molded body opposite the first surface. The second portion of the signal pin of the plurality of signal pins include is internal to the electronic device assembly, is electrically coupled with the patterned metal layer, and is electrically continuous with the first portion.

    STRAY INDUCTANCE REDUCTION IN PACKAGED SEMICONDUCTOR DEVICES
    7.
    发明申请
    STRAY INDUCTANCE REDUCTION IN PACKAGED SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210066256A1

    公开(公告)日：2021-03-04

    申请号：US16671450

    申请日：2019-11-01

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Seungwon IM ,  ByoungOk LEE ,  Oseob JEON

    IPC分类号： H01L25/07 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

    摘要： In a general aspect, a semiconductor device can include a substrate and a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane. The device can also include a first negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The device can further include a second negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The positive power supply terminal can be disposed between the first and second negative power supply terminals. The device can also include a conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge. A portion of the conductive bridge can be arranged in a second plane that is parallel to, and non-coplanar with the first plane.

    FLUIDIC-CHANNEL COOLED SUBSTRATES
    9.
    发明公开
    FLUIDIC-CHANNEL COOLED SUBSTRATES 审中-公开

    公开(公告)号：US20240194564A1

    公开(公告)日：2024-06-13

    申请号：US18444251

    申请日：2024-02-16

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Jihwan KIM ,  Oseob JEON ,  Seungwon IM ,  Dongwook KANG

    IPC分类号： H01L23/473 ,  H01L23/15 ,  H01L23/31 ,  H01L25/065

    CPC分类号： H01L23/473 ,  H01L23/15 ,  H01L23/3121 ,  H01L25/0652

    摘要： In a general aspect, a semiconductor device module includes a ceramic substrate having a first surface and a second surface opposite the first surface, a patterned metal layer disposed on the first surface of the ceramic substrate, a semiconductor die disposed on the patterned metal layer, and a cooling structure disposed on the second surface of the ceramic substrate. The cooling structure includes a plurality of copper sheets defining a plurality of fluidic-cooling channels. At least one copper sheet of the plurality of copper sheets is at least one of coated or plated with a corrosion-resistant material. The module also includes a molding compound that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die. The molding compound also partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.

    SWITCHING OSCILLATION REDUCTION FOR POWER SEMICONDUCTOR DEVICE MODULES
    10.
    发明公开
    SWITCHING OSCILLATION REDUCTION FOR POWER SEMICONDUCTOR DEVICE MODULES 审中-公开

    公开(公告)号：US20240138069A1

    公开(公告)日：2024-04-25

    申请号：US18491456

    申请日：2023-10-19

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Oseob JEON ,  Seungwon IM ,  Rajani Kumar THIRUKOLURI ,  Roveendra PAUL

    IPC分类号： H05K1/18 ,  H05K1/11

    CPC分类号： H05K1/18 ,  H05K1/11 ,  H05K2201/10166

    摘要： In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.