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公开(公告)号:US20240332128A1
公开(公告)日:2024-10-03
申请号:US18129567
申请日:2023-03-31
发明人: Cyprian Emeka Uzoh , Belgacem Haba , Rajesh Katkar
IPC分类号: H01L23/46 , H01L23/367 , H01L23/433
CPC分类号: H01L23/46 , H01L23/367 , H01L23/433
摘要: Embodiments herein provide for device packages comprising an integrated cooling assembly and methods of cooling packaged devices. The integrated cooling assembly comprising a semiconductor device, a manifold attached to the semiconductor device, and a sonic transducer attached to the manifold. The manifold comprises a top portion and a waveguide extending downwardly from the top portion. The sonic transducer is attached to the top portion. The top portion, the waveguide, and a backside of the semiconductor device collectively define a coolant chamber volume therebetween.
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公开(公告)号:US12100636B2
公开(公告)日:2024-09-24
申请号:US17327027
申请日:2021-05-21
IPC分类号: H01L23/367 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/13 , H01L23/31 , H01L23/373 , H01L23/42 , H01L23/433
CPC分类号: H01L23/3672 , H01L21/4871
摘要: The present application relates to a chip heat dissipating structure, a chip structure, a circuit board and a supercomputing device, and the chip heat dissipating structure includes a metal layer, where the metal layer is covered on the chip. By adding a metal layer on the top of the chip, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip; the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, thus improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip.
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公开(公告)号:US20240282668A1
公开(公告)日:2024-08-22
申请号:US18172904
申请日:2023-02-22
发明人: Yong LIU , Liangbiao CHEN , Yusheng LIN , Chee Hiong CHEW
IPC分类号: H01L23/433 , H01L21/48 , H01L21/56 , H01L23/31
CPC分类号: H01L23/4334 , H01L21/4882 , H01L21/565 , H01L23/3107
摘要: A protective dam can relieve stress in a chip assembly of a high-power semiconductor device module used in electric vehicle or industrial applications. Some chip assemblies that incorporate copper spacers for thermal dissipation can cause the device module to become vulnerable to cracking. Adding a protective dam can absorb stress to prevent damage to materials surrounding the chip assembly. Various types of protective dams are presented, including high profile flexible protective dams, low profile flexible protective dams, metallic protective dams, and integral protective dams. The protective dams can be incorporated into a high-power semiconductor device module that features single sided or dual sided cooling via direct bond metal structures.
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公开(公告)号:US12068217B2
公开(公告)日:2024-08-20
申请号:US17612218
申请日:2019-07-26
发明人: Takashi Nishimura , Hiroki Shiota
IPC分类号: H01L23/373 , H01L21/48 , H01L23/00 , H01L23/16 , H01L23/31 , H01L23/367 , H01L23/433 , H01L23/495 , H02P27/08
CPC分类号: H01L23/3733 , H01L21/481 , H01L21/4871 , H01L23/16 , H01L23/3121 , H01L23/367 , H01L23/4334 , H01L23/49562 , H01L24/32 , H01L24/73 , H01L24/84 , H01L2924/181 , H02P27/08
摘要: A semiconductor device includes a semiconductor module, an insulating resin layer, a frame member, and a heat sink. Insulating resin layer is bonded to semiconductor module and contains a first resin. Frame member is disposed to surround insulating resin layer, and includes a porous material. Heat sink and semiconductor module sandwich insulating resin layer and frame member. Frame member is compressed while being sandwiched between semiconductor module and heat sink. Insulating resin layer is filled in a region surrounded by semiconductor module, heat sink, and frame member. The first resin enters pores of the porous material.
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公开(公告)号:US20240274505A1
公开(公告)日:2024-08-15
申请号:US18330233
申请日:2023-06-06
发明人: Shuai-Lin LIU , Nai-Hao KAO , Yu-Po WANG
IPC分类号: H01L23/433 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/16
CPC分类号: H01L23/4334 , H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L25/0655 , H01L25/16 , H01L24/32 , H01L2224/19 , H01L2224/211 , H01L2224/214 , H01L2224/215 , H01L2224/32225 , H01L2924/01029
摘要: An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in an encapsulation layer, and a circuit structure is disposed on the encapsulation layer and electrically connected to the first electronic element and the second electronic element. The circuit structure has a hollow area corresponding to the first electronic element, and a heat dissipation structure is disposed in the hollow area to thermally connect the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation structure, so as to avoid the problem of affecting the operation of the second electronic element due to the overheating of the encapsulation layer.
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公开(公告)号:US20240222223A1
公开(公告)日:2024-07-04
申请号:US18092136
申请日:2022-12-30
IPC分类号: H01L23/46 , H01L23/367 , H01L23/433 , H01L25/065
CPC分类号: H01L23/46 , H01L23/3677 , H01L23/4332 , H01L25/0655
摘要: An exemplary apparatus includes a substrate; a plurality of chips mounted onto the substrate; a plurality of cold plates corresponding to the plurality of chips; means for pressing each of the cold plates toward a corresponding one of the chips; means for delivering coolant flow to the cold plates; and means for adjusting the cooling power of the plurality of cold plates, responsive to at least one sensed parameter of the plurality of chips.
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公开(公告)号:US20240222221A1
公开(公告)日:2024-07-04
申请号:US18149617
申请日:2023-01-03
申请人: NVIDIA Corporation
发明人: Padam Jain , Ronilo Boja
IPC分类号: H01L23/427 , H01L21/48 , H01L23/433
CPC分类号: H01L23/427 , H01L21/4882 , H01L23/433 , H01L24/16
摘要: An IC package including an IC and a TIM assembly located on the IC. The TIM assembly includes a lid defining a compartment, a mixed-phase material located in the compartment, the mixed-phase material including nanostructures, and a liquid metal occupying open spaces in the compartment that are not occupied by the nanostructures. A method of manufacturing an IC package, including providing the IC and placing the TIM assembly on the IC. A computer having one or more circuits that include the IC package.
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公开(公告)号:US20240194563A1
公开(公告)日:2024-06-13
申请号:US18201466
申请日:2023-05-24
发明人: Hyunggyun Noh , Jinsoo Bae , Il-Joo Choi
IPC分类号: H01L23/433 , H01L21/56 , H01L23/00
CPC分类号: H01L23/4334 , H01L21/56 , H01L24/13 , H01L24/16 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/16227
摘要: A semiconductor package includes: a substrate; a semiconductor chip provided on the substrate; a plurality of heat dissipation reinforcements provided on the substrate; and an encapsulant, on the substrate, molding the semiconductor chip and the plurality of heat dissipation reinforcements. Each of the plurality of heat dissipation reinforcements has an elongated shape, and extends along lateral surfaces and an upper surface of the semiconductor chip at a predetermined interval from the semiconductor chip.
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公开(公告)号:US20240170367A1
公开(公告)日:2024-05-23
申请号:US18472350
申请日:2023-09-22
申请人: DENSO CORPORATION
发明人: Yoichi SASAKI , Satoru WAKIYAMA
IPC分类号: H01L23/433 , H01L21/56 , H01L23/14 , H01L23/31 , H01L23/538
CPC分类号: H01L23/4334 , H01L21/568 , H01L23/145 , H01L23/3107 , H01L23/5386 , H01L23/5389
摘要: A semiconductor device includes: a die; a mold material layer in which the die is embedded in a state where an electrode surface of the die is exposed from the mold material layer; and a redistribution layer provided on a surface of the mold material layer and having an insulating layer and a wiring in a multilayer state, as a fan out wafer level package. The wiring of the redistribution layer has a reinforcing portion that is thicker in a thickness direction within an area corresponding to a boundary region between the die and the mold material layer than the other area.
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公开(公告)号:US20240071860A1
公开(公告)日:2024-02-29
申请号:US18502162
申请日:2023-11-06
发明人: Yusheng LIN , Jerome TEYSSEYRE
IPC分类号: H01L23/373 , H01L21/52 , H01L23/00 , H01L23/31 , H01L23/433 , H01L23/498 , H01L25/00 , H01L25/065 , H01L25/07
CPC分类号: H01L23/3735 , H01L21/52 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/3135 , H01L23/4334 , H01L23/49822 , H01L24/20 , H01L25/0657 , H01L25/072 , H01L25/50 , H01L29/861
摘要: In a general aspect, a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.
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