公开(公告)号：US20240355779A1

公开(公告)日：2024-10-24

申请号：US18763686

申请日：2024-07-03

申请人： Samsung Electronics Co., Ltd.

发明人： Hyeonseok LEE ,  Jongyoun KIM ,  Seokhyun LEE

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L25/0655 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16014 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2924/182

摘要： A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

公开(公告)号：US12119238B2

公开(公告)日：2024-10-15

申请号：US16588588

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L21/563 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/06181 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13172 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13172 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/11

摘要： A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

公开(公告)号：US12100680B2

公开(公告)日：2024-09-24

申请号：US17846125

申请日：2022-06-22

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Luguang Wang ,  Jinrong Huang

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/16147 ,  H01L2224/81895 ,  H01L2924/04941 ,  H01L2924/04953

摘要： A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.

公开(公告)号：US20240297086A1

公开(公告)日：2024-09-05

申请号：US18116268

申请日：2023-03-01

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chun-Wei CHIANG ,  Yun-Ching HUNG ,  Yung-Sheng LIN

IPC分类号： H01L23/10 ,  H01L21/50

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204

摘要： An interconnection structure and a package structure are provided. The interconnection structure includes a substrate, a conductive layer, a bonding layer, and a moderating layer. The conductive layer is over the substrate and has a top surface. The bonding layer is over the top surface of the conductive layer. The moderating layer is between the conductive layer and the bonding layer and configured to mitigate an increase in a surface roughness of the top surface of the conductive layer during an electroless plating process for forming the bonding layer.

公开(公告)号：US20240282743A1

公开(公告)日：2024-08-22

申请号：US18654268

申请日：2024-05-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L25/10

CPC分类号： H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L25/105 ,  H01L24/03 ,  H01L24/11 ,  H01L24/20 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13019 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/27462 ,  H01L2224/29026 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81121 ,  H01L2224/81125 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/8191 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/15311 ,  H01L2924/181

摘要： A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

公开(公告)号：US20240065003A1

公开(公告)日：2024-02-22

申请号：US18295324

申请日：2023-04-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dongkyu KIM ,  Kyounglim SUK ,  Hyeonseok LEE ,  Hyeonjeong HWANG

IPC分类号： H10B80/00 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31

CPC分类号： H10B80/00 ,  H01L23/5226 ,  H01L24/16 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/16145 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/13124 ,  H01L2224/13155 ,  H01L2224/1318 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13171 ,  H01L2224/13111 ,  H01L2224/13166 ,  H01L2224/1146

摘要： A semiconductor package includes a memory chip having chip pads on a first surface thereof. A redistribution layer is formed on the first surface of the memory chip. The redistribution layer is electrically connected to the chip pads. The redistribution layer has first redistribution pads on a first surface of the redistribution layer in a first region and a plurality of second redistribution pads on the first surface of the redistribution layer in a second region thereof. A processor chip is disposed on the first region of the redistribution layer and is electrically connected to the first redistribution pads. A sealing member is disposed on the first surface of the redistribution layer and covers the processor chip. Conductive structures are on the second region and penetrate through the sealing member and extend upwardly in a vertical direction away from the second redistribution pads.

公开(公告)号：US11894330B2

公开(公告)日：2024-02-06

申请号：US17209113

申请日：2021-03-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hao-Yi Tsai

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/13 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06051 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13026 ,  H01L2224/1357 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/14051 ,  H01L2224/16058 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01322 ,  H01L2924/3512 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/00014 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05555 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13169 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/13026 ,  H01L2924/00012 ,  H01L2224/13616 ,  H01L2924/014 ,  H01L2224/13611 ,  H01L2924/014 ,  H01L2224/81416 ,  H01L2924/014 ,  H01L2224/81411 ,  H01L2924/014 ,  H01L2224/81444 ,  H01L2924/014 ,  H01L2224/81447 ,  H01L2924/014 ,  H01L2224/81455 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

公开(公告)号：US11855038B2

公开(公告)日：2023-12-26

申请号：US17432354

申请日：2020-02-20

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Olivier Castany ,  Nohora-Lizeth Caicedo Panqueva ,  Nadia Miloud-Ali ,  Yezouma-dieudonne Zonou

IPC分类号： H01L23/00 ,  B23K1/20 ,  H05K3/34 ,  B23K101/40

CPC分类号： H01L24/81 ,  B23K1/206 ,  H01L24/13 ,  H01L24/16 ,  H05K3/3489 ,  B23K2101/40 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13644 ,  H01L2224/16145 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81022 ,  H01L2224/81075 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/014 ,  H05K2203/0285

摘要： A method for assembling components includes assembling a first component including solder bumps with a second component including connectors. The assembly of the components is preceded by pre-treating the first and second components wherein the solder bumps are contacted with a pre-treatment liquid configured to at least partially remove an oxide layer initially present on the solder. The pre-treatment liquid is an aqueous solution containing carboxylic acids or polycarboxylic acids. The assembly of the components is carried out after the pre-treatment in the absence of liquid or gas flux.

公开(公告)号：US20230380302A1

公开(公告)日：2023-11-23

申请号：US18357814

申请日：2023-07-24

申请人： SeeQC, Inc.

发明人： Daniel Yohannes ,  Denis Amparo ,  Oleksandr Chernyashevskyy ,  Oleg Mukhanov ,  Mario Renzullo ,  Andrei Talalaeskii ,  Igor Vernik ,  John Vivalda ,  Jason Walter

IPC分类号： H10N60/81 ,  H01L23/00 ,  H10N60/12 ,  H10N60/01

CPC分类号： H10N60/815 ,  H01L24/13 ,  H01L24/81 ,  H01L24/05 ,  H10N60/12 ,  H10N60/0912 ,  H01L2924/0495 ,  H01L2224/0401 ,  H01L2224/05179 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13179 ,  H01L2224/8109 ,  H01L2224/8112 ,  H01L2224/81203 ,  H01L2924/04941

摘要： A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

公开(公告)号：US11810881B2

公开(公告)日：2023-11-07

申请号：US18073295

申请日：2022-12-01

申请人： ROHM CO., LTD.

发明人： Bungo Tanaka ,  Keiji Wada ,  Satoshi Kageyama

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L23/3107 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1318 ,  H01L2224/13018 ,  H01L2224/1357 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13647 ,  H01L2224/293 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/181 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/293 ,  H01L2924/00014 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/48465 ,  H01L2224/48227 ,  H01L2924/00

摘要： A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.