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公开(公告)号：US20240355886A1
公开(公告)日：2024-10-24
申请号：US18760960
申请日：2024-07-01
Applicant: ROHM CO., LTD.
Inventor： Yasuhiro KAWAKAMI
IPC: H01L29/16 , H01L21/04 , H01L29/417 , H01L29/47 , H01L29/66 , H01L29/872
CPC classification number: H01L29/1608 , H01L21/0495 , H01L29/417 , H01L29/47 , H01L29/66143 , H01L29/872 , H01L2224/02166 , H01L2224/04042 , H01L2224/05083 , H01L2224/05139 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05558 , H01L2224/05567 , H01L2224/05583 , H01L2224/05624 , H01L2224/05644 , H01L2224/05666 , H01L2224/0568 , H01L2224/06181 , H01L2924/10272 , H01L2924/12032 , H01L2924/351
Abstract: A semiconductor device according to the present invention includes a first conductive-type Sic semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.
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公开(公告)号：US12002725B2
公开(公告)日：2024-06-04
申请号：US18199215
申请日：2023-05-18
Applicant: Amkor Technology Singapore Holding Pte. Ltd.
Inventor： Ji Young Chung , Dong Joo Park , Jin Seong Kim , Jae Sung Park , Se Hwan Hong
IPC: H01L23/15 , G06V40/13 , H01L23/00 , H01L21/56 , H01L23/31 , H01L23/495 , H01L23/498
CPC classification number: H01L23/15 , G06V40/1329 , H01L24/48 , H01L21/561 , H01L23/3121 , H01L23/4952 , H01L23/49805 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/02166 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/2919 , H01L2224/32225 , H01L2224/33181 , H01L2224/48091 , H01L2224/48105 , H01L2224/48165 , H01L2224/48227 , H01L2224/48992 , H01L2224/48997 , H01L2224/73215 , H01L2224/73265 , H01L2224/8592 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/15313 , H01L2924/181 , H01L2224/97 , H01L2224/83 , H01L2224/97 , H01L2224/85 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/45099 , H01L2224/05647 , H01L2924/00015 , H01L2224/05624 , H01L2924/00015 , H01L2224/05639 , H01L2924/00015 , H01L2224/05644 , H01L2924/00015 , H01L2224/05655 , H01L2924/00015 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/92247 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/2919 , H01L2924/00014 , H01L2224/48091 , H01L2924/00014
Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.
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公开(公告)号：US11990434B2
公开(公告)日：2024-05-21
申请号：US17714830
申请日：2022-04-06
Applicant: ROHM CO., LTD.
Inventor： Kazuki Yoshida , Hajime Kataoka
IPC: H01L23/00 , H01L23/31 , H01L23/495
CPC classification number: H01L24/05 , H01L23/3107 , H01L23/49513 , H01L23/4952 , H01L23/49524 , H01L23/49562 , H01L24/03 , H01L2224/02166 , H01L2224/02181 , H01L2224/02185 , H01L2224/0219 , H01L2224/03013 , H01L2224/03848 , H01L2924/07025
Abstract: A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface facing one side in a thickness direction, and a first electrode arranged on the element main surface; a first insulating layer that is arranged over a peripheral edge portion of the first electrode and the element main surface and includes a first annular portion formed in an annular shape when viewed in the thickness direction; and a second insulating layer that is laminated on the first insulating layer, is made of a resin material, and includes a second annular portion overlapping with the first annular portion when viewed in the thickness direction.
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公开(公告)号：US11764343B2
公开(公告)日：2023-09-19
申请号：US16982217
申请日：2019-12-19
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhiwei Liang , Yingwei Liu , Zhijun Lv , Ke Wang , Zhanfeng Cao , Hsuanwei Mai , Guangcai Yuan , Muxin Di
IPC: H01L33/62 , H01L23/00 , H01L25/075
CPC classification number: H01L33/62 , H01L24/03 , H01L24/05 , H01L25/0753 , H01L2224/0219 , H01L2224/02166 , H01L2224/02185 , H01L2224/03013 , H01L2224/03462 , H01L2224/03614 , H01L2224/03622 , H01L2224/0401 , H01L2224/05017 , H01L2224/0518 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2933/0066
Abstract: A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.
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5.发明申请
公开(公告)号：US20190115481A1
公开(公告)日：2019-04-18
申请号：US16210131
申请日：2018-12-05
Applicant: ROHM CO., LTD.
Inventor： Hiroki YAMAMOTO
IPC: H01L29/872 , H01L29/66 , H01L29/861 , H01L27/06 , H01L49/02 , H01L29/417 , H01L23/00 , H01L27/102 , H01L23/544 , H01L29/06 , H01L29/866 , H01L23/522 , H01L23/495 , H01L27/07
CPC classification number: H01L29/872 , H01L23/3114 , H01L23/3192 , H01L23/49551 , H01L23/49562 , H01L23/5223 , H01L23/5228 , H01L23/544 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L27/0255 , H01L27/0629 , H01L27/067 , H01L27/0722 , H01L27/1021 , H01L28/10 , H01L28/20 , H01L28/24 , H01L28/40 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/417 , H01L29/66136 , H01L29/861 , H01L29/8611 , H01L29/866 , H01L2223/54413 , H01L2223/54433 , H01L2223/54473 , H01L2223/54493 , H01L2224/02166 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05144 , H01L2224/05553 , H01L2224/05567 , H01L2224/05624 , H01L2224/05644 , H01L2224/06181 , H01L2224/11009 , H01L2224/11464 , H01L2224/13022 , H01L2224/131 , H01L2224/16225 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/73253 , H01L2224/73265 , H01L2224/85205 , H01L2224/94 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/12035 , H01L2924/12036 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2924/014 , H01L2224/11 , H01L2924/00 , H01L2224/45015 , H01L2924/207
Abstract: A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.
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公开(公告)号：US20190107575A1
公开(公告)日：2019-04-11
申请号：US16211882
申请日：2018-12-06
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto PAGANI
CPC classification number: G01R31/2884 , H01L22/32 , H01L22/34 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05554 , H01L2924/12042 , H01L2924/00
Abstract: A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure TEG realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.
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公开(公告)号：US20180182690A1
公开(公告)日：2018-06-28
申请号：US15851007
申请日：2017-12-21
Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
Inventor： Li Zhong JIN , Li Hui LU , Chun Chao FEI , Po Yuan CHIANG , Ya Ping WANG
IPC: H01L23/49 , H01L23/485 , H01L23/00 , H01L21/02
CPC classification number: H01L23/49 , H01L21/02123 , H01L23/485 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/02166 , H01L2224/0345 , H01L2224/0361 , H01L2224/05098 , H01L2224/05166 , H01L2224/05181 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05624 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45184 , H01L2224/48463 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/1032 , H01L2924/10329 , H01L2924/1033 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01008
Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.
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公开(公告)号：US20180145001A1
公开(公告)日：2018-05-24
申请号：US15876833
申请日：2018-01-22
Applicant: Renesas Electronics Corporation
Inventor： Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe
CPC classification number: H01L22/32 , G01R31/26 , H01L22/14 , H01L22/20 , H01L22/30 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/02166 , H01L2224/02313 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/06133 , H01L2224/06135 , H01L2224/10 , H01L2224/1132 , H01L2224/11334 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/4911 , H01L2224/49429 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/85951 , H01L2225/0651 , H01L2225/06517 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/12041 , H01L2924/1306 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2224/48744 , H01L2924/00012
Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
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9.发明申请
公开(公告)号：US20180138227A1
公开(公告)日：2018-05-17
申请号：US15849403
申请日：2017-12-20
Applicant: CANON KABUSHIKI KAISHA
Inventor： Mineo Shimotsusa , Takeshi Ichikawa , Yasuhiro Sekine
IPC: H01L27/146 , H01L31/024 , H01L23/00
CPC classification number: H01L27/14634 , H01L24/05 , H01L27/14618 , H01L27/14621 , H01L27/14687 , H01L27/1469 , H01L31/024 , H01L2224/02166 , H01L2224/04042 , H01L2224/48463 , H01L2924/12042 , H01L2924/12043 , H01L2924/13091 , H01L2924/351 , H01L2924/00
Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.
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公开(公告)号：US20180108626A1
公开(公告)日：2018-04-19
申请号：US15642742
申请日：2017-07-06
Applicant: International Business Machines Corporation
Inventor： Ekta Misra , Krishna R. Tunga
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/0215 , H01L2224/02166 , H01L2224/02185 , H01L2224/0219 , H01L2224/03013 , H01L2224/0401 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05191 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05657 , H01L2224/05666 , H01L2224/05669 , H01L2224/0567 , H01L2224/05676 , H01L2224/05681 , H01L2224/05684 , H01L2224/05687 , H01L2224/05691 , H01L2224/05693 , H01L2224/131 , H01L2224/13111 , H01L2924/07025 , H01L2924/3511 , H01L2924/35121 , H01L2924/014 , H01L2924/01047 , H01L2924/00014 , H01L2924/04953 , H01L2924/04941 , H01L2924/0455 , H01L2924/01073 , H01L2924/04541 , H01L2924/0469 , H01L2924/0463 , H01L2924/01013 , H01L2924/0476 , H01L2924/01074 , H01L2924/0496 , H01L2924/0538 , H01L2924/01044 , H01L2924/0479 , H01L2924/01027 , H01L2924/048 , H01L2924/01028 , H01L2924/01006
Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
